Split-Entry DRAM Cache for Continuous Multi-Bank Line Bursts
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Solution Overview
Problem
Existing DRAM cache architectures struggle with inefficiencies in handling cache line transfers due to mismatched data input/output widths between DRAM cores and host processors, leading to latency and bandwidth limitations.
Innovation Solution
Implementing a DRAM cache architecture that splits cache entries across multiple DRAM storage banks, utilizing time-staggered access operations to enable back-to-back data transfers, allowing continuous cache line bursts that match the host processor's requirements, while optimizing tag and status information storage to facilitate rapid hit/miss determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM cache architecture uses single-entry storage per cache line, then storage simplicity is maintained, but data transfer bandwidth and speed are limited due to mismatched data input/output widths
Solution Approach 1:
The patent divides each cache entry into multiple sub-entries distributed across different DRAM storage banks. Each sub-entry stores a portion of the cache line data, allowing parallel retrieval from multiple banks simultaneously. This segmentation enables the system to achieve higher data transfer bandwidth by reading multiple cache line fragments in parallel, directly resolving the contradiction between data transfer capability and storage simplicity.
Solution Approach 2:
The patent introduces a temporal dimension to data retrieval by implementing time-staggered access operations. Instead of sequential reading, the system activates multiple storage banks at different time intervals within a single cache access cycle, enabling back-to-back data transfers without idle gaps. This dimensional approach to time management maximizes bandwidth utilization while maintaining manageable architectural complexity through structured bank grouping.
2Speed
If time-staggered access operations are implemented, then continuous data bursts are enabled, but access control complexity increases
Solution Approach 1:
The patent implements preliminary bank pairing and grouping before data access operations. Storage banks are pre-configured into pairs and groups with predetermined activation timing sequences. This preliminary organization eliminates the need for complex real-time scheduling during cache accesses, as the time-staggered activation pattern is already established. The access control mechanism simply follows the pre-defined sequence to retrieve data from paired banks, achieving high transfer speeds without proportionally increasing control complexity.
3Productivity
If cache entries are split across multiple banks, then bandwidth is maximized, but hit/miss determination time increases
Solution Approach 1:
The patent stores tag information and metadata associated with cache entries in the same storage banks where the data is distributed. Before initiating data retrieval, the system activates the relevant storage banks and retrieves tag information in parallel with the data fetch operations. This preliminary preparation of access control information allows the hit/miss determination to proceed simultaneously with data transfer, rather than sequentially, thereby maintaining fast determination times while achieving high bandwidth through multi-bank data splitting.
Data Source
AI summary
A high-capacity cache memory is implemented by one or more DRAM dies in which individual cache entries are split across multiple DRAM storage banks such that each cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry.