Split-Gate Transistor Control for Active Clamp Tolerance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving both low ON resistance and high active clamp tolerance, as adjusting the channel area for one parameter often compromises the other, leading to a tradeoff.
Innovation Solution
A semiconductor device is designed with a split-gate transistor, an active clamp circuit, and a gate control circuit that gradually increases the ON resistance after switching from the ON to the OFF state, allowing for effective voltage limiting and maintaining low ON resistance while enhancing active clamp tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel area of the transistor is increased to reduce ON resistance, then the ON resistance decreases, but the active clamp tolerance deteriorates
Solution Approach 1:
The patent applies dynamics by making the transistor resistance time-dependent rather than static. The resistance is low during normal operation to minimize power loss, then gradually increases after switching to protect against active clamp voltage spikes. This dynamic adjustment resolves the contradiction between maintaining low ON resistance and providing high active clamp tolerance.
Solution Approach 2:
The gate control circuit performs preliminary action by proactively increasing the transistor resistance after switching occurs, before the active clamp circuit needs to limit the output voltage. This preventive measure prepares the system in advance to handle voltage spikes, resolving the contradiction by establishing protection before the harmful condition arises.
2Object-affected harmful factors
If the channel area is decreased to improve active clamp tolerance, then the active clamp tolerance improves, but the ON resistance increases
Solution Approach 1:
The patent uses dynamics to make the resistance adaptive rather than fixed. Instead of permanently increasing resistance to improve active clamp tolerance, the system maintains low resistance during normal operation and only increases it when needed after switching. This resolves the contradiction by providing high active clamp tolerance only when required, without sacrificing normal ON resistance performance.
Solution Approach 2:
The gate control circuit implements periodic action by cyclically adjusting the transistor resistance based on operational phase. During the ON state, resistance remains low for efficient power conduction; after switching to OFF state, resistance gradually increases to protect against voltage spikes. This periodic adjustment resolves the contradiction by optimizing resistance for each operational phase.
Data Source
AI summary
A semiconductor device 1 includes: a split-gate transistor 9 connected between a drain electrode 11 (output electrode OUT) and a ground electrode and having a plurality of individually controllable channel regions; an active clamp circuit 26 configured to limit the output voltage VOUT appearing at the output electrode 11 to a clamp voltage or below; and a gate control circuit 25 configured to raise the ON resistance of the split-gate transistor 9 gently (or stepwise) after the split-gate transistor is switched from the ON state to the OFF state before the active clamp circuit 26 limits the output voltage VOUT.