Split-Gate Trench MOS Transistor Body Self-Alignment
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Solution Overview
Problem
The misalignment between the body region and gate regions in MOS transistors due to etching variations in the formation of insulating layers leads to increased gate/drain capacitance and drain/source on-state resistance, adversely affecting the switching frequency and Safe Operating Area (SOA) of the MOS transistor.
Innovation Solution
A self-alignment process is employed by implanting dopants along tilted directions to form the body region, ensuring it aligns in depth with the gate regions, using a combination of silicon oxide and silicon nitride layers to control the implantation path and achieve precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching process is used to form insulating layers, then manufacturing process is simple, but misalignment between body region and gate regions occurs leading to increased gate/drain capacitance and drain/source on-state resistance
Solution Approach 1:
The patent applies preliminary action by forming the body region first through tilted dopant implantation before forming the gate regions. This sequence ensures that the body region is already in place at the correct depth and orientation, allowing subsequent gate formation to automatically align with it. The tilted implantation angle (e.g., 45 degrees) is specifically chosen to ensure the body region forms at the precise depth where gate regions will later be positioned, eliminating alignment issues that would otherwise require complex etching processes.
2Manufacturing precision
If tilted dopant implantation is used to form body region, then alignment with gate regions is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies self-service by using the tilted dopant implantation process to automatically self-align the body region with the subsequently formed gate regions. The tilted angle of implantation causes the dopants to reach a specific depth that corresponds exactly to where the gate regions will be formed, without requiring additional alignment steps or complex etching processes. The process serves itself by using the implantation geometry to inherently define the alignment, eliminating the need for separate alignment procedures.
3Ease of manufacture
If misalignment between body region and gate regions occurs, then manufacturing is easier, but gate/drain capacitance and drain/source on-state resistance increase
Solution Approach 1:
The patent applies preliminary action by forming the body region first through tilted dopant implantation before forming the gate regions. This sequence ensures that the body region is already in place at the correct depth and orientation, allowing subsequent gate formation to automatically align with it. The tilted implantation angle (e.g., 45 degrees) is specifically chosen to ensure the body region forms at the precise depth where gate regions will later be positioned, eliminating alignment issues that would otherwise require complex etching processes.
Solution Approach 2:
The patent applies self-service by using the tilted dopant implantation process to automatically self-align the body region with the subsequently formed gate regions. The tilted angle of implantation causes the dopants to reach a specific depth that corresponds exactly to where the gate regions will be formed, without requiring additional alignment steps or complex etching processes. The process serves itself by using the implantation geometry to inherently define the alignment, eliminating the need for separate alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This alignment reduces variations in gate/drain capacitance and drain/source on-state resistance, enhancing the switching frequency and SOA of the MOS transistor.
Implementation Method 1
implanting dopants along one or more implantation directions that are tilted with respect to a front surface of the die
Data Source
AI summary
A process is proposed for manufacturing an integrated device having at least one MOS transistor integrated on a die of semiconductor material. The process includes forming one or more gate trenches with corresponding field plates and gate regions. A body region is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface of the die. Moreover, a corresponding integrated device and a system comprising this integrated device are proposed.


