Split-Gate Trench MOSFET Etching for CD and Aspect Ratio Control
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Solution Overview
Problem
Prior semiconductor devices face limitations in minimum contact CD control and silicon etch aspect ratio, which hinder the performance of split gate trench MOSFETs in achieving low RDSON capabilities at respective reverse breakdown voltages.
Innovation Solution
The method involves etching trenches in two steps, with the second trench being wider and deeper than the first, using a hard mask and nitride spacer, and applying anisotropic and isotropic etching, along with thermal annealing, to create a more narrow silicon region between trenches, enhancing the reverse breakdown voltage and On-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single trench is etched with conventional methods, then the manufacturing process is simple, but the minimum contact CD control and silicon etch aspect ratio are limited
Solution Approach 1:
The trench etching process is divided into two separate etching steps: first etching a initial trench, then etching a second trench from the bottom side to create an overlapping region. This segmentation allows independent optimization of each etching step's parameters, enabling better control over the final contact CD and etch aspect ratio while managing process complexity through systematic division of the manufacturing process
Solution Approach 2:
The patent introduces a vertical dimension to the etching process by etching the second trench from the bottom side upward, creating an overlapping region with the first trench. This dimensional approach allows precise control of the contact CD by adjusting the overlap depth, transforming a horizontal width control problem into a vertical depth control problem that is more manageable with existing etching tools
2Reliability
If the trench width is reduced to improve device performance, then the reverse breakdown voltage improves, but the etch aspect ratio becomes more difficult to control
Solution Approach 1:
By segmenting the trench formation into two steps with different widths, the patent achieves a narrow effective trench width in the overlapping region (improving reverse breakdown voltage) while maintaining a wider opening in the first trench (improving etch aspect ratio). Each etching step operates with optimized dimensions, resolving the contradiction between narrow trench requirements and etchability requirements
Solution Approach 2:
The patent creates different trench width characteristics at different vertical positions: the upper portion has a wider width for easy etching, while the lower overlapping region has a narrower width for improved breakdown voltage. This local variation in trench geometry allows simultaneous optimization of both etch aspect ratio and reverse breakdown voltage performance
3Reliability
If conventional single-trench etching is used, then the process is straightforward, but the On-state resistance performance is limited
Solution Approach 1:
The dual-trench etching process creates distinct regions that can be independently optimized for different device functions, enabling improved On-state resistance performance through better control of the contact geometry and doping profiles while managing complexity through systematic process division
Solution Approach 2:
The patent changes key geometric parameters by creating an overlapping trench structure where the second trench overlaps with the first trench. This parameter change enables optimization of the contact CD and etch aspect ratio independently, leading to improved On-state resistance performance through better control of current flow paths and contact geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reverse breakdown voltage and On-state resistance capabilities of semiconductor devices by controlling trench dimensions and reducing etch defects, thereby enhancing the performance of split gate trench MOSFETs.
Implementation Method 1
forming an oxide layer on the first trench walls
Implementation Method 2
depositing a nitride layer on the oxide layer on the at least first trench walls
Implementation Method 3
sacrificial oxide growth on the sidewalls of the first trench and/or the second trench to reduces the etch defects
Implementation Method 4
providing an epitaxial, EPI, layer with substrate
Data Source
Figure 1
Figure 2(a)~2(f)
Figure 3(g)~3(l)
AI summary
Proposed is a method of manufacturing a semiconductor trench-gate semiconductor device comprising a trench divided into a first trench and a second trench and wherein the source poly is arranged in the second trench and a gate poly is arranged in the first trench and separated from the source poly by means of an inter poly oxide layer. The width of the second trench is larger than the width of the first trench and the depth of the second trench is larger than the depth of the first trench and the liner oxide layer is thicker than the gate oxide layer. Also, the ratio between the first trench width A and the second trench width B is in range from 1:1,7 to 1:2.