Split-Gate Trench MOSFET Layout for Small Cell Pitch
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Solution Overview
Problem
Existing power trench MOSFET devices face challenges in achieving stable breakdown voltage and high cell density due to high parasitic capacitance and input capacitance, which affect switching characteristics and power consumption.
Innovation Solution
A semiconductor device with a split gate trench structure, where a shield electrode is formed at the lower portion of the trench and a gate electrode at the upper portion, with optimized thickness ratios and inter-electrode insulating layers to reduce parasitic capacitance and input capacitance, allowing for improved switching characteristics and cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes are formed on both sides of the upper portion of the shield poly electrode in a triple poly structure, then the breakdown voltage can be maintained, but the parasitic capacitance between the gate electrode and source electrode increases
Solution Approach 1:
The gate electrode structure is segmented into two separate electrodes (first gate electrode and second gate electrode) positioned at different locations within the trench. This segmentation allows each gate electrode to be independently optimized for its specific function, reducing the overall parasitic capacitance while maintaining breakdown voltage requirements
Solution Approach 2:
The patent transitions from a planar gate electrode configuration to a three-dimensional trench structure with gate electrodes positioned at different vertical and horizontal locations. This dimensional change enables better spatial separation between gate electrodes and source electrode, reducing parasitic capacitance while maintaining electrical performance
2Object-generated harmful factors
If the thickness of the insulating layer between the gate poly electrode and shield poly electrode is increased to reduce parasitic capacitance, then the parasitic capacitance value decreases, but the trench width increases making it difficult to secure small cell pitch
Solution Approach 1:
The insulating layer thickness is optimized locally at critical interfaces rather than uniformly throughout the structure. The patent uses selective insulation thickness and material composition at specific locations to reduce parasitic capacitance without requiring overall increase in trench width, thereby maintaining high cell density
Solution Approach 2:
The patent employs composite insulating layer structures with different materials having varying dielectric properties. By combining materials with different electrical characteristics, the design achieves low parasitic capacitance with thinner overall insulation, preserving small cell pitch while reducing harmful capacitance effects
3Reliability
If two gate poly electrodes are formed on both sides of the top of the shield electrode in a triple poly structure, then the breakdown voltage is secured, but the input capacitance (Ciss) increases resulting in increased switching loss
Solution Approach 1:
The patent extracts and separates the gate electrode functions into distinct first and second gate electrodes positioned at different locations. This extraction allows optimization of each electrode's contribution to breakdown voltage while minimizing their combined contribution to input capacitance, thereby reducing switching losses
Solution Approach 2:
The patent optimizes parameters including gate electrode thickness, insulating layer thickness, and electrode positioning to achieve the desired balance between breakdown voltage and input capacitance. By carefully controlling these parameters, the design maintains reliability while minimizing energy loss during switching operations
Data Source
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AI summary
A semiconductor device includes: a semiconductor substrate; an epitaxial layer disposed on the substrate; a plurality of trenches formed in the epitaxial layer; a shield insulating layer formed inside the plurality of trenches; a shield electrode surrounded by the shield insulating layer and disposed inside the plurality of trenches; an inter-electrode insulating layer formed on top of the shield insulating layer and the shield electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; a body region formed on an upper portion of the epitaxial layer located between the plurality of trenches; a source region formed on the body region; an inter-layer insulating layer formed on the gate electrode and the source region; and a body contact region in contact with the source region and the body region.