Split-Gate Dielectric Structure for High Voltage EDMOS Devices
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Solution Overview
Problem
High voltage extended drain MOSFET devices require advanced gate dielectric materials and structures to maintain performance at smaller technology nodes, such as below 40 nm, while ensuring high voltage capabilities and efficient SiGe channel formation.
Innovation Solution
The implementation of a split-gate dielectric structure with a thinner second gate dielectric material and a high-k dielectric material on top, along with a high voltage gate oxide serving as a hard mask for SiGe formation, allows for the integration of high-k metal gate (HKMG) platforms in CMOS field effect transistors, enabling devices to operate up to 20 volts with thin and thick oxide combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate dielectric structure is used in MOSFET devices at smaller technology nodes (below 40 nm), then manufacturing simplicity is maintained, but voltage handling capability and device performance deteriorate
Solution Approach 1:
The gate dielectric is segmented into multiple layers: a first gate dielectric layer (thicker, providing voltage handling), a second gate dielectric layer (thinner, enabling SiGe channel formation), and a high-k dielectric layer (enhancing gate control). This segmentation allows each layer to fulfill specific functional requirements that cannot be met by a single conventional gate dielectric layer.
Solution Approach 2:
The gate dielectric structure uses composite materials combining different dielectric properties. The first gate dielectric (e.g., thicker oxide) provides high breakdown voltage, the second gate dielectric (e.g., thinner oxide) enables effective SiGe channel formation, and the high-k dielectric (e.g., HfO2) provides enhanced gate control with lower leakage. This composite structure achieves both high voltage capability and improved device performance.
2Adaptability or versatility
If a single gate oxide layer is used, then device structure simplicity is maintained, but the ability to form SiGe channels and handle high voltages simultaneously is compromised
Solution Approach 1:
Different regions of the gate dielectric structure have different thicknesses and materials optimized for local requirements. The second gate dielectric layer is positioned where SiGe channel formation is needed, with a thinner thickness to allow effective interface formation. The first gate dielectric layer provides thicker protection in regions requiring high voltage handling. This local quality variation enables simultaneous SiGe channel formation and high voltage capability.
Data Source
AI summary
The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.