Split Gate Device Doped Region Charge Shielding
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Solution Overview
Problem
In split gate devices, charge trap-up due to trapped charges in the dielectric of the charge storage layer, particularly at the source edge, negatively impacts the threshold voltage and is difficult to remove during cycling, necessitating an improved design to reduce these effects.
Innovation Solution
A selective implant of dopants is performed through part of the control gate layer near the source edge to create doped regions that shield trapped charges, reducing their influence on the device's electrical characteristics. This is achieved by controlling the implant's energy and timing, and using anti-reflective coatings and spacers to prevent damage and ensure proper placement of dopants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge storage layer is used in split gate devices, then nonvolatile memory storage capability is improved, but trapped charges accumulate in the dielectric causing threshold voltage degradation
Solution Approach 1:
The patent extracts or removes the harmful trapped charges from the dielectric layer through selective doping. By introducing dopants into specific regions, the trapped charges are neutralized or extracted, eliminating their harmful effect on threshold voltage while preserving the charge storage functionality of the memory device.
Solution Approach 2:
The patent converts the harmful trapped charges into a beneficial effect by using dopants to create regions that actively counteract the trapped charges. The doping process transforms the problematic charge accumulation into a controlled electrical characteristic that can be used to stabilize threshold voltage and improve device reliability.
2Productivity
If device size is reduced to increase integration density, then productivity is improved, but charge trap-up effects become more significant
Solution Approach 1:
The patent applies local quality by implementing selective doping in specific regions rather than uniformly across the entire device. By targeting particular areas with dopants, the solution addresses charge trap-up locally where it occurs most severely, allowing the device to maintain small dimensions while compensating for trap-up effects in a localized manner.
Solution Approach 2:
The patent changes electrical parameters through doping to counteract the effects of charge trap-up. By modifying the dopant concentration and distribution in specific regions, the electrical characteristics are adjusted to compensate for trap-up, enabling smaller device dimensions without sacrificing reliability.
3Object-generated harmful factors
If dopants are implanted through the control gate layer, then trapped charges are shielded, but device structure complexity increases
Solution Approach 1:
The patent segments the doping process into multiple controlled steps with different dopant types, concentrations, and implantation conditions. This segmentation allows precise control over dopant distribution to effectively shield trapped charges while managing process complexity through systematic, staged implementation rather than a single complex step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The doped regions effectively shield trapped charges, reducing their impact on the device's performance and improving the reliability of split gate devices by minimizing the effects of trap-up.
Implementation Method 1
A selective implant of dopants is performed through part of the control gate layer near the source edge to create doped regions that shield trapped charges
Data Source
AI summary
A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.