Split-Gate Semiconductor Device Fabrication Using Dual Hard Masks
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Solution Overview
Problem
Conventional methods for forming split-gate semiconductor structures struggle to minimize the size of the select gate while maintaining its performance, as the width of the upper portion of the select gate becomes too narrow, affecting its properties and performance.
Innovation Solution
The use of two hard masks to define the widths of the control and select gates, allowing for precise control and adjustment of the select gate width during the etching process, ensuring the upper portion maintains an appropriate width and performance even during miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the width of the select gate is minimized to reduce device size, then the overall device size is reduced, but the width of the upper portion of the select gate becomes too narrow to maintain its properties and performance
Solution Approach 1:
The patent divides the gate structure into two separate gates: a control gate and a select gate, positioned at different locations. This segmentation allows each gate to be independently optimized for its specific function, enabling the select gate to maintain adequate width for performance while the overall device size is minimized through the split-gate configuration
Solution Approach 2:
The patent transitions from a single gate structure to a split-gate structure where the select gate is positioned laterally offset from the control gate. This dimensional rearrangement allows the select gate to have sufficient width for proper operation while the overall footprint is optimized, resolving the contradiction between size minimization and performance maintenance
2Ease of manufacture
If conventional anisotropic etch process is used to form select gate, then the fabrication process is simple, but the shape of the select gate is difficult to control and the upper portion width cannot be increased
Solution Approach 1:
The patent forms spacers on the gate structure before defining the final select gate pattern. These pre-formed spacers serve as templates that guide subsequent etching processes, enabling precise control of the select gate shape and dimensions while maintaining a relatively simple overall fabrication sequence
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between the gate formation and final select gate definition. These spacers act as temporary structures that control the etching process, enabling precise shape control of the select gate while keeping the fabrication process manageable
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.