Split-Gate EEPROM With Isolated Well Structures
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Solution Overview
Problem
Existing EEPROMs have low area utilization due to interference between mirrored floating-gate store positions, leading to erroneous erasure and inefficient operation.
Innovation Solution
The EEPROM design includes split-gate storage cells with separate doping type well structures, allowing independent voltage control for each store position to prevent interference, improving area utilization by eliminating the need for additional gating transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If split-gate structures with mirrored floating-gates are used, then over-erase effect is avoided and circuit design is simplified, but area utilization is reduced due to interference between the two floating-gates
Solution Approach 1:
The patent divides the well structure into multiple isolated segments using isolation structures. Each segment contains one or more floating-gates that can be independently controlled without interfering with adjacent segments. This segmentation allows both floating-gates in a split-gate structure to function independently, resolving the interference problem while maintaining the area efficiency of the split-gate design.
Solution Approach 2:
The patent introduces isolation structures as intermediary elements between adjacent floating-gates and well regions. These isolation structures act as mediators that prevent electrical interference and charge leakage between neighboring storage elements, enabling reliable independent operation of each floating-gate while maintaining compact layout.
2Reliability
If two floating-gates are used in each split-gate structure, then over-erase protection is achieved, but only one store position can be effectively used due to interference
Solution Approach 1:
By segmenting the well structure into isolated regions, the patent enables each floating-gate to operate as an independent store position. The isolation structures prevent charge tunneling and electrical interference between adjacent floating-gates, allowing both store positions in each split-gate structure to be actively used for data storage and operations simultaneously.
Solution Approach 2:
The patent applies different electrical characteristics to different regions through the isolation structures. Each isolated well segment has localized electrical properties that prevent interference with neighboring segments, allowing each floating-gate to maintain its own charge state independently and enabling both store positions to function effectively.
3Reliability
If additional gating transistors are added to prevent interference, then store position isolation is achieved, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical/electrical control approach (using additional gating transistors) with a structural isolation approach. By using isolation structures to physically and electrically separate well regions, the patent achieves store position isolation without requiring additional active control elements, thereby reducing device complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances area utilization by ensuring accurate erasure, programming, and reading operations without interference between store positions, reducing the overall area required for EEPROM operations.
Implementation Method 1
every N columns of the plurality of split-gate storage cells are formed on one first well structure, and adjacent first well structures are separated by a second well structure having a different doping type with that of the first well structures
Implementation Method 2
a voltage difference between the first well voltage and the erasure voltage makes electrons stored on the first store position be erased
Data Source
AI summary
An EEPROM and methods for erasing, programming and reading it, the EEPROM includes a plurality of split-gate storage arrays, each of the plurality of split-gate storage cells including a source connected with a first bit line, a drain connected with a second bit line, a first control gate connected with a first store position, a word line gate connected with a word line and a second control gate connected with a second store position; and the first control gate is connected with a first control gate line, and the second control gate is connected with a second control gate line, wherein every N columns of the split-gate storage cells are formed on a first well structure, adjacent first well structures are separated by a second well structures having a different doping type with that of the first well structures, and N is a positive integer.