Split-Gate FinFET DRAM Back-Gate Leakage Control
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Solution Overview
Problem
Conventional DRAM devices face challenges in reducing operating power due to leakage issues, which conflicts with the need for lower threshold voltage to minimize power consumption, especially as semiconductor sizes decrease and single gate devices experience performance degradation.
Innovation Solution
The implementation of a split-gate DRAM with a FinFET structure, where a back-gate is connected to a conducting layer of the substrate, allowing for controlled threshold voltage and simultaneous control of multiple devices, operating in modes to reduce leakage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the threshold voltage is reduced to lower wordline voltage and operating power, then power consumption decreases, but leakage increases significantly
Solution Approach 1:
The gate is divided into two independent gates: a front gate and a back gate. The front gate controls the primary channel conduction, while the back gate independently controls the threshold voltage to suppress leakage. This segmentation allows separate optimization of power consumption and leakage control without the trade-off present in single-gate devices.
Solution Approach 2:
The back gate voltage is dynamically adjusted to modify the threshold voltage of the FinFET. By changing the electrical parameter (gate voltage) of the back gate, the threshold voltage can be optimized to minimize leakage while maintaining low operating power, effectively decoupling the previously conflicting parameters.
2Loss of energy
If the threshold voltage is kept high to prevent leakage, then leakage is reduced, but wordline voltage must be high increasing power consumption
Solution Approach 1:
The gate is divided into two independent gates: a front gate and a back gate. The front gate controls the primary channel conduction, while the back gate independently controls the threshold voltage to suppress leakage. This segmentation allows separate optimization of power consumption and leakage control without the trade-off present in single-gate devices.
Solution Approach 2:
The back gate voltage is dynamically adjusted to modify the threshold voltage of the FinFET. By changing the electrical parameter (gate voltage) of the back gate, the threshold voltage can be optimized to minimize leakage while maintaining low operating power, effectively decoupling the previously conflicting parameters.
3Device complexity
If single gate devices are used to maintain simple structure, then device complexity is low, but performance degrades at smaller sizes
Solution Approach 1:
The gate is divided into two independent gates: a front gate and a back gate. The front gate controls the primary channel conduction, while the back gate independently controls the threshold voltage to suppress leakage. This segmentation allows separate optimization of power consumption and leakage control without the trade-off present in single-gate devices.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional FinFET structure with gates on opposite sides of the fin. This dimensional change provides superior electrostatic control and performance at scaled dimensions while maintaining a relatively simple manufacturing process compared to other multi-gate configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-power operation while maintaining dense array configurations by controlling the back-gate's electrical potential, reducing subthreshold channel leakage and the required wordline voltage during read/write operations.
Implementation Method 1
a back-gate at a first lateral side of the fin and in electrical contact with the conductive region... controlling the back-gate's electrical potential, reducing subthreshold channel leakage
Implementation Method 2
a storage capacitor connected to a first end of the fin... the threshold voltage of the fin of the FinFET retards leakage of stored charge out of the capacitance structure
Data Source
AI summary
A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at a first lateral side of the fin and in electrical contact with the conductive region.