3D Split-Gate FinFET Memory Cell for Higher Current Flow
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Solution Overview
Problem
As semiconductor device geometries shrink, the reduced channel width in split-gate non-volatile memory cells leads to decreased current flow, requiring more sensitive sense amplifiers, and existing Fin-FET structures with multiple gates or complex configurations have not adequately addressed this issue while maintaining device footprint.
Innovation Solution
A Fin-FET configuration with a simple split gate structure, featuring a floating gate and a control gate with specific extensions, is developed, utilizing silicon trench etching and partial oxide fill for isolation, and self-aligned components to enhance capacitive coupling and current flow without increasing semiconductor real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device geometries are shrunk to reduce area, then semiconductor real estate is reduced, but channel width decreases leading to reduced current flow
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure with a fin-shaped body extending vertically from the substrate. This vertical dimension allows the channel to utilize both top and side surfaces, effectively increasing the channel width and current flow capacity without occupying additional planar area on the semiconductor substrate.
2Reliability
If FinFET structure is used to increase channel width, then current flow increases, but device complexity increases with multiple gates or trapping materials
Solution Approach 1:
The control gate is segmented into two distinct portions: a first portion positioned laterally adjacent to the floating gate, and a second portion extending vertically over the floating gate. This segmentation allows independent control of different channel regions, enabling sophisticated memory operations while maintaining a relatively simple overall structure without requiring multiple separate gates or complex trapping material systems.
Solution Approach 2:
The patent implements a nested gate configuration where the second portion of the control gate extends over and encapsulates the floating gate in the vertical dimension. This nested arrangement allows the control gate to effectively control the channel while the floating gate performs charge storage, achieving complex functionality through spatial nesting rather than separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases current flow by expanding the channel region's width on the top and side surfaces of the fin-shaped channel, enhancing capacitive coupling and maximizing current flow with smaller device components, while maintaining efficient processing and self-aligned memory cell formation.
Implementation Method 1
Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces
Implementation Method 2
forming a gate dielectric layer on exposed portion of the active region to cover exposed side surfaces of the of charge storage layer
Implementation Method 3
forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region
Data Source
Figure 1A~2A
Figure 1B~2B
Figure 1C~2C
AI summary
A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.