Split-Gate FinFET Flash Memory for Density and Leakage Control
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Solution Overview
Problem
Existing non-volatile flash memory cell technologies face challenges in scaling down size due to issues with ultra-thin polysilicon or amorphous silicon film deposition, non-uniform doping, structural non-uniformities, increased capacitive coupling, and complex design requirements for high-speed access times, leading to reduced read currents and increased leakage.
Innovation Solution
A memory cell design featuring a split-gate architecture with fins extending along opposing side surfaces and a top surface, where the floating gate is positioned at the intersections of these fins, allowing for improved control of channel regions and reduced leakage, and utilizing a high K dielectric material for the word line gate to enhance performance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down in size, then density increases, but read currents decrease and leakage increases
Solution Approach 1:
The patent transitions from planar floating gate memory cells to FinFET-based vertical structures. The channel region is formed as a fin extending vertically from the substrate, with the floating gate wrapping around the fin in a three-dimensional configuration. This vertical dimensionality increase allows for increased channel width and read current without increasing the planar footprint, thereby maintaining density while improving electrical performance.
Solution Approach 2:
The floating gate is configured to wrap around the fin structure in a nested arrangement. The insulator layer is deposited conformally around the fin, and the floating gate material is deposited to surround the fin vertically and laterally. This nested configuration maximizes the channel width while minimizing the planar area, enabling high density with improved current characteristics.
2Length of moving object
If ultra-thin polysilicon or amorphous silicon films are used, then device size is reduced, but doping uniformity and structural uniformity deteriorate
Solution Approach 1:
The patent changes the material parameter from ultra-thin polysilicon or amorphous silicon to crystalline silicon for the fin structure. Crystalline silicon provides superior structural uniformity and doping characteristics. The fin is formed by etching through the crystalline silicon substrate, which maintains atomic-level structural uniformity even at reduced dimensions, thereby improving doping uniformity and overall manufacturing precision.
3Area of stationary object
If horizontal scaling is performed, then device area is reduced, but capacitive coupling between neighboring floating gates increases
Solution Approach 1:
The patent separates neighboring memory cells in the vertical dimension rather than relying solely on horizontal spacing. The floating gates are positioned at different vertical levels around the fins, and the insulator layers provide vertical isolation. This three-dimensional separation reduces the capacitive coupling between adjacent cells that occurs when cells are packed closely in the planar direction, thereby reducing cross-talk while maintaining high density.
4Ease of manufacture
If planar floating gate architecture is used, then manufacturing is simpler, but sub-threshold leakage control deteriorates
Solution Approach 1:
The patent employs a vertical FinFET architecture where the channel current flows along the vertical fin structure. The floating gate wraps around the fin in a three-dimensional configuration, providing control over the channel from multiple directions. This vertical configuration enhances the control of sub-threshold leakage current compared to planar devices, as the electric field distribution and channel confinement are improved in the vertical dimension, while the manufacturing process remains compatible with standard CMOS techniques.
Data Source
Figure 1A
Figure 1B~1C
Figure 1D~1E
AI summary
A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.