Split-Gate Memory and FinFET Integration on a Shared Wafer
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Solution Overview
Problem
Existing methods face challenges in simultaneously forming non-volatile memory cells, high voltage devices, and FINFET logic devices on the same wafer substrate without adverse effects on each other, due to shared processing steps that can compromise device quality.
Innovation Solution
A method involving a silicon substrate with recessed areas for different device types, using polysilicon layers and etching processes to form trenches and fins, followed by insulation and implantation steps to create source and drain regions, and finally forming high K material and metal blocks for enhanced device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shared processing steps are used for forming gates of both memory cells and logic devices, then manufacturing complexity is reduced, but device quality and reliability deteriorate due to adverse effects between device types
Solution Approach 1:
The substrate is divided into distinct device regions (memory cell region, logic device region, high voltage device region) with different surface heights. Each region is processed independently at its appropriate height level, allowing different processing conditions for each device type while maintaining a unified manufacturing flow. The recess isolation structures create physical segmentation that prevents adverse interactions between processing steps for different device types.
Solution Approach 2:
Different regions of the substrate are given different local properties through selective recessing. The memory cell and high voltage device regions have recessed surfaces with isolation structures, while the logic device region maintains a higher surface level. This allows each region to have optimized processing conditions and structural characteristics suited to its specific device type requirements.
2Power
If FinFET structures are used to increase effective channel width, then current flow increases, but fabrication complexity increases due to additional processing steps
Solution Approach 1:
The FinFET fin formation process is merged with the logic device gate formation process. The same polysilicon deposition and patterning steps that form the logic device gates also define the FinFET fin structures. The recessed isolation structures are formed before FinFET processing, allowing fins to be etched from the higher surface region without requiring separate isolation formation steps, thereby reducing overall fabrication complexity while achieving enhanced current flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the concurrent formation of high-performance non-volatile memory cells, high voltage devices, and FINFET logic devices with improved fabrication techniques, reducing the footprint and enhancing channel control while maintaining operational efficiency.
Implementation Method 1
forming first trenches through the first polysilicon layer and into the silicon substrate in the first and second areas but not in the third area, using at least a first silicon etch; after the forming of the fin, forming second trenches into the silicon substrate in the third area using at least a second silicon etch
Implementation Method 2
performing a first implantation to form a first source region in the silicon substrate in the first area between the pair of floating gates; performing one or more implantations to form: a first drain region in the first area of the substrate adjacent the second polysilicon block, a second drain region in the first area of the substrate adjacent the third polysilicon block, a second source region in the second area of the substrate adjacent the fourth polysilicon block, a third drain region in the second area of the substrate adjacent the fourth polysilicon block, a third source region in the fin adjacent the fifth polysilicon block, and a fourth drain region in the fin adjacent the fifth polysilicon block
Data Source
Figure 1A~2C
Figure 3A~4C
Figure 5A~6C
AI summary
A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.