Split-Gate FinFET Memory Cells With Higher Channel Current
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Solution Overview
Problem
As semiconductor device geometries shrink, the channel region width in split gate non-volatile memory devices decreases, reducing current flow and requiring more sensitive sense amplifiers, while Fin-FET structures attempt to address this by increasing channel width by 'folding' it into side surfaces, but previous Fin-FET memory cell configurations are complex and inefficient.
Innovation Solution
A memory device with Fin-FET split gate type cells featuring a floating gate, control gate, select gate, and erase gate extending along the side and top surfaces of fins, allowing for increased channel region surface area without sacrificing semiconductor real estate, and a method for forming these cells and logic devices on the same substrate with recessed fins to enhance current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device geometries are shrunk to reduce memory cell footprint, then area is reduced, but channel width decreases and current flow reduces
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure where the channel is formed as a vertical fin extending from the substrate. This dimensional change allows the channel to provide current flow path in the vertical dimension while maintaining a small horizontal footprint, effectively resolving the contradiction between reduced area and maintained current flow.
Solution Approach 2:
The patent implements a nested gate structure where multiple gates (select gate, erase gate, control gate, and floating gate) are positioned at different vertical levels around the fin channel. This nesting arrangement allows all four gates to control the same vertical channel without requiring additional horizontal space, enabling compact memory cell design with sufficient current flow.
2Reliability
If Fin-FET structure is used to increase channel width by folding into side surfaces, then current flow increases, but device complexity increases
Solution Approach 1:
The patent divides the gate control function into four separate gate structures (select gate, erase gate, control gate, and floating gate) positioned at different vertical levels. Each gate segment performs a specific function, allowing the complex control requirements to be distributed across multiple simpler components rather than requiring a single complex gate structure.
Solution Approach 2:
The vertical fin channel serves multiple functions simultaneously: it provides the current flow path, acts as the storage node interface, and enables compact stacking of multiple gates. This multi-functional use of the FinFET structure reduces overall device complexity by eliminating the need for separate structures for each function.
3Reliability
If floating gate is disposed adjacent to one side surface of fin, then current flow increases, but footprint is not optimized
Solution Approach 1:
The patent positions the floating gate and other gates in the vertical dimension rather than spreading them out horizontally. By stacking the gates at different heights around the fin, the design achieves high current flow through the vertical channel while maintaining minimal horizontal footprint, effectively resolving the area-current flow contradiction.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.