Split Gate FinFET Layout for Analog Design Mismatch Reduction
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Solution Overview
Problem
In analog circuit designs, particularly in fin field effect transistor (finFET) circuits, device mismatch due to variations in device width and length, as well as random dopant fluctuation and shot noise, leads to performance degradation, especially as device size decreases, making it challenging to achieve low variance in threshold voltage among transistors.
Innovation Solution
The implementation of a split gate structure in finFET devices, where the gate is divided into multiple regions with additional dopants injected between these regions, maintains the desired width and length while increasing the number of dopants, thereby minimizing device mismatch and improving pattern density uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is decreased to increase density, then device density is improved, but device mismatch increases
Solution Approach 1:
The gate structure is divided into multiple segments (first gate region, second gate region, third gate region) separated by gaps. This segmentation allows independent optimization of each gate region and enables the insertion of additional dopant regions between gate segments, effectively increasing the total number of dopants in a compact area without increasing overall device footprint.
Solution Approach 2:
The patent introduces dopant regions in the vertical dimension between horizontally arranged gate regions, transitioning from a two-dimensional planar layout to a three-dimensional structure. This allows additional dopants to be added without increasing the lateral device area, thereby maintaining high density while improving matching precision.
2Area of stationary object
If device size is decreased to increase density, then layout area is reduced, but threshold voltage variance increases
Solution Approach 1:
Different regions of the device are assigned different functions: gate regions provide electrical control, gaps provide space for additional dopants, and dopant regions provide localized charge compensation. This local differentiation allows each region to be optimized for its specific purpose, improving overall device performance and reducing threshold voltage variance within a compact layout.
Solution Approach 2:
The device structure combines multiple materials and regions: semiconductor material for the substrate, conductive material for gates, and doped regions with different doping concentrations. This composite structure enables fine-tuned control of electrical properties and threshold voltage matching without increasing device area.
3Manufacturing precision
If number of dopants is increased to reduce mismatch, then device matching is improved, but device complexity increases
Solution Approach 1:
Multiple functional elements are merged into a single integrated structure: the segmented gate regions, gap regions, and dopant regions are combined in a unified device architecture. This merging achieves improved device matching through increased dopant count while avoiding the complexity of separate, discrete components, as all elements are formed in an integrated manner within the single device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device mismatch and variance in threshold voltage, enhancing circuit performance by increasing the number of dopants, which decreases the standard deviation of shot noise and improves layout efficiency and uniformity.
Implementation Method 1
a diffusion region formed on the semiconductor substrate and extending through the diffusion layer
Implementation Method 2
Dopants are injected into the diffusion layer to form a diffusion region having a plurality of pocket dopant regions
Data Source
AI summary
A method of forming a finFET includes providing a semiconductor substrate having at least one fin feature extending through a diffusion layer formed on the semiconductor substrate, forming a gate layer on the diffusion layer and the fin feature, splitting the gate layer into a split gate structure including a first gate region, a second gate region, and a gap separating the first gate region and the second gate region, doping the gate layer, doping the diffusion layer to form a plurality of source/drain regions that includes a source/drain region in the gap between the first gate region and the second gate region, and injecting dopants into the diffusion layer to form a diffusion region having a plurality of pocket dopant regions. The plurality of pocket dopant regions includes at least one pocket dopant region in the gap between the first gate region and the second gate region.