Split Gate FinFET Transistors for SRAM Area Optimization
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Solution Overview
Problem
Conventional integrated circuit (IC) designs face challenges in adding transistors without increasing die area and cost, particularly in bulk silicon substrates, where dual pass gate devices are not feasible due to area and cost constraints.
Innovation Solution
The method involves forming integrated circuits with a combination of split gate FinFET and common gate FinFET devices using semiconductor fins of varying heights, where a split gate electrode is created on taller fins and a common gate electrode on shorter fins, allowing for parallel transistors to be formed within the same or similar die area as conventional FinFETs, utilizing selective fin etching and chemical-mechanical polishing for gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual pass gate devices are added to optimize read and write operations in SRAM cells, then circuit performance is improved, but die area increases leading to higher cost
Solution Approach 1:
The gate structure is segmented into two separate gates (first gate and second gate) that can be independently controlled, allowing dual pass gate functionality to be achieved within a single FinFET device footprint, thus improving circuit performance without increasing die area
Solution Approach 2:
The invention utilizes the vertical dimension by forming fins perpendicular to the substrate surface, allowing the gate electrodes to wrap around the fin structure in three dimensions. This enables dual gate control within the same planar footprint, resolving the contradiction between enhanced performance and area constraints
2Power
If FinFETs with larger width conduction channel are used to produce larger current drive, then transistor performance is improved, but die area increases
Solution Approach 1:
The conduction channel is oriented vertically along the fin height rather than horizontally in the plane of the substrate. This three-dimensional configuration allows the channel width to extend vertically, providing larger current drive capability while maintaining the same planar footprint as conventional planar FETs
Data Source
AI summary
An integrated circuit includes common gate FinFET and split gate FinFET devices formed from different height fins at a semiconductor surface of a substrate. A patterned layer of gate electrode material formed over sides and unconnected over the tops of the taller fins defines respective gate electrodes for first and second paired transistors. The patterned layer of gate electrode material formed over the sides and connected over tops of the shorter fins defines common gate electrodes for transistors. In one embodiment, the common gate devices are used for cross-coupled inverters of a memory cell core storage element and the split gate devices are used for pass gates, with the gate electrodes coupled to wordlines and common source/drains coupled to bitline/complementary bitline and core element storage/complementary storage nodes.In another embodiment, the split gate devices are used for input transistors of a differential amplifier, with one gate electrode coupled to receive an input signal and the other gate electrode coupled to receive a mismatch correction bias.