Planar Split-Gate Memory and FinFET Logic Co-Integration Layout
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Solution Overview
Problem
The challenge lies in simultaneously forming non-volatile flash memory cells and high voltage transistors with low voltage FinFET transistors on the same silicon chip, as existing methods often complicate the process due to shared processing steps that can adversely affect one another.
Innovation Solution
A method involving a silicon substrate with distinct areas for memory cells, high voltage devices, and logic devices, where recessing and polysilicon deposition techniques are used to form specific gate structures, including floating gates, erase gates, and logic gates, while maintaining insulation and channel regions to accommodate different device types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple device types (memory cells, high voltage transistors, low voltage FinFET transistors) are formed on the same wafer, then device integration and productivity are improved, but processing complexity and manufacturing precision deteriorate due to adverse processing effects between different device structures
Solution Approach 1:
The wafer is divided into distinct processing zones with different depth levels. Memory cell regions and high voltage transistor regions are recessed to a first depth, while FinFET logic device regions extend to a second, greater depth. This spatial segmentation allows each device type to undergo optimized processing without adverse interactions from conflicting structure requirements.
Solution Approach 2:
The patent introduces a vertical depth dimension to differentiate processing zones. By creating recessed regions at one depth level and extending other regions to a greater depth, the patent adds a vertical stratification that enables simultaneous formation of multiple device types with different structural requirements on the same wafer surface.
2Reliability
If FinFET structures are used to increase effective channel width, then current flow and device performance are improved, but manufacturing precision and processing difficulty worsen due to the complex three-dimensional structure formation
Solution Approach 1:
Mandrel structures are formed first in the FinFET regions before the actual FinFET structures are created. These mandrels serve as templates that guide subsequent processing steps, including anisotropic etching to form the vertical fins and lateral overgrowth to create the three-dimensional channel structure. This preliminary templating action simplifies the precision requirements of later steps.
Solution Approach 2:
Mandrel structures act as intermediary elements that mediate between the planar substrate and the final three-dimensional FinFET structure. The mandrels provide a simplified intermediate form that can be easily formed with standard lithography, then transformed into the complex FinFET geometry through controlled etching and overgrowth processes.
3Adaptability or versatility
If different gate stack thicknesses and topologies are accommodated for different device types, then device versatility and functionality are improved, but manufacturing complexity and process steps worsen
Solution Approach 1:
Different regions of the wafer are given different local properties through selective recessing and extending. Memory cell and high voltage transistor regions have recessed upper surfaces suitable for planar gate stacks, while FinFET logic device regions have extended surfaces suitable for three-dimensional gate structures. This local differentiation allows each device type to have optimized gate stack characteristics without requiring global process changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the effective integration of FinFET-based memory cells and high voltage devices with logic devices, enhancing operational performance and simplifying manufacturing by using common processing steps and materials, while maintaining the integrity of each device type.
Implementation Method 1
forming a floating gate disposed over and insulated from a first portion of the first channel region of the substrate using a first polysilicon deposition; forming an erase gate disposed over and insulated from the first source region and a device gate disposed over and insulated from the third channel region of the substrate using a second polysilicon deposition different from the first polysilicon deposition
Implementation Method 2
forming a word line gate disposed over and insulated from a second portion of the first channel region, a control gate disposed over and insulated from the floating gate, and a logic gate disposed over and insulated from the second channel region of the substrate, using a metal deposition
Data Source
AI summary
A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.