FinFET Memory Logic Devices Split Gate Non-Volatile
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Solution Overview
Problem
Existing technologies face challenges in simultaneously forming non-volatile flash memory cells, high voltage transistor devices, and logic devices on the same wafer substrate without adversely affecting each other, particularly in sharing processing steps and achieving optimal channel width and footprint.
Innovation Solution
A method involving a silicon substrate with recessed areas, implantations to form source and drain regions, and polysilicon depositions to create floating, control, and erase gates, along with metal depositions for word and logic gates, allowing for the formation of FinFET-type memory cells and logic devices alongside high voltage transistor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFET type structure is used to increase effective channel width, then current flow is increased, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple surfaces (top surface and two side surfaces of the fin shaped member) to increase effective channel width. This segmentation allows current to flow through multiple paths simultaneously, achieving higher current flow without requiring a single excessively wide planar channel.
Solution Approach 2:
The channel region is folded from a two-dimensional planar structure into a three-dimensional FinFET structure with vertical fins. This dimensional transformation creates additional current flow paths along the side surfaces of the fins, effectively increasing channel width without proportionally increasing the device footprint or overall complexity.
2Productivity
If multiple device types are formed on the same wafer, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
Different regions of the wafer are assigned different device configurations: FinFET structures for memory cells and logic devices requiring high current flow, and planar structures for high voltage transistor devices requiring different electrical characteristics. This local differentiation allows each device type to be optimized for its specific function while sharing common processing steps.
Solution Approach 2:
The wafer is segmented into different device regions (memory cell areas, logic device areas, and high voltage transistor areas) that can undergo different processing sequences. This segmentation enables selective formation of FinFET structures in some regions while maintaining planar structures in others, preserving manufacturing precision for each device type.
3Area of stationary object
If channel region is folded into side surfaces, then footprint is reduced, but device complexity increases
Solution Approach 1:
The channel region utilizes the vertical dimension by forming fins that extend upward from the substrate. Current flows along the side surfaces of these vertical fins, effectively packing more channel length and width into a smaller planar footprint. This three-dimensional configuration reduces the area occupied on the wafer surface.
Solution Approach 2:
The FinFET structure nests multiple channel surfaces (top and two sides) within a compact vertical architecture. This nesting of current flow paths within the fin structure achieves high effective channel width without proportionally increasing the device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and effective formation of memory cells and logic devices with enhanced channel control and reduced footprint, facilitating common processing steps and improved operational performance.
Implementation Method 1
performing a first implantation to form a first source region in the first area of the substrate; performing a second implantation to form a first drain region in the first area of the substrate and to form a second source region and a second drain region in the third area of the substrate
Implementation Method 2
forming a floating gate disposed over and insulated from a first portion of the first channel region using a first polysilicon deposition; forming a control gate disposed over and insulated from the floating gate using a second polysilicon deposition; forming an erase gate disposed over and insulated from the first source region and a device gate disposed over and insulated from the second channel region using a third polysilicon deposition
Data Source
AI summary
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.