Split-Gate Flash Memory Array Byte Erase Subsource Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing split gate non-volatile memory arrays require erasing an entire row of memory cells to change information, lacking the ability to selectively erase just a portion of a row, which is inefficient for updating single bytes of information.
Innovation Solution
The memory array architecture is modified to include sub source lines and select transistors that allow for selective erasure of a subrow of memory cells by applying specific voltages, enabling the erasure of a single subrow without affecting other memory cells in the row or array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the entire row of memory cells is erased to change information, then the memory cell can be reprogrammed, but the erasure operation is inefficient when only a single byte needs to be updated
Solution Approach 1:
The source line is divided into multiple independently controllable sub-source lines, each corresponding to a specific column or group of columns. By activating only the sub-source line associated with the target byte, the erasure operation is segmented to affect only the desired portion of the memory array, thereby improving data update efficiency and reducing unnecessary erasure time.
Solution Approach 2:
Different sub-source lines are selectively activated based on the specific column or group of columns that need to be erased. This local control mechanism ensures that only the targeted region undergoes erasure, while other regions remain unaffected, optimizing the erasure operation for partial updates.
2Productivity
If the entire row is erased to update a single byte, then all memory cells in the row are reset, but unnecessary memory cells are reprogrammed
Solution Approach 1:
The source line is divided into multiple independently controllable sub-source lines, each corresponding to a specific column or group of columns. By activating only the sub-source line associated with the target byte, the erasure operation is segmented to affect only the desired portion of the memory array, thereby improving data update efficiency and reducing unnecessary erasure time.
Solution Approach 2:
Different sub-source lines are selectively activated based on the specific column or group of columns that need to be erased. This local control mechanism ensures that only the targeted region undergoes erasure, while other regions remain unaffected, optimizing the erasure operation for partial updates.
3Adaptability or versatility
If sub source lines and select transistors are added to enable selective erasure, then byte-level erasure is achieved, but the device complexity increases
Solution Approach 1:
The source line is divided into multiple independently controllable sub-source lines, each corresponding to a specific column or group of columns. By activating only the sub-source line associated with the target byte, the erasure operation is segmented to affect only the desired portion of the memory array, thereby improving data update efficiency and reducing unnecessary erasure time.
Solution Approach 2:
The sub-source lines and select transistors serve multiple functions: they enable selective erasure operations, provide column selection capability, and maintain compatibility with existing word line and bit line structures. This multi-functionality justifies the added complexity by providing versatile control over memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for precise erasure of a portion of a row, enhancing data update efficiency and reducing unnecessary reprogramming of the entire row, while maintaining the programming state of other memory cells.
Implementation Method 1
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling.
Implementation Method 2
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. This technique is often referred to as hot electron injection.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.