Split Gate Flash Cell Architecture for Compact Array Design
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Solution Overview
Problem
Split gate flash memory cells face challenges with increased cell size due to dedicated select and erase gate structures, leading to higher cell resistance and susceptibility to corner rounding effects, which limit downscaling and increase channel resistance.
Innovation Solution
The architecture employs isolated source regions diffused only between stacked control gate structures, eliminating the need for a common source under isolation regions, and uses a metal layer for potential coupling during programming and erasing to reduce resistance and cell size, thereby suppressing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated select and erase gate structures are used in split gate flash memory cells, then over erase immunity is improved, but cell size increases
Solution Approach 1:
The patent merges the select gate and erase gate functions into a single stacked gate structure where the control gate serves dual purposes. This integration eliminates the need for separate dedicated select and erase gate structures, thereby reducing cell size while maintaining over erase immunity through the split gate architecture.
Solution Approach 2:
The control gate in the stacked gate structure is designed to perform multiple functions - acting as both the select gate for channel formation and the erase gate for charge removal. This multi-functionality allows the cell to maintain reliability features of split gate structures while minimizing the area occupied by gate structures.
2Area of stationary object
If common source region is extended under isolation regions to reduce cell size, then area overhead is reduced, but corner rounding effects increase channel resistance
Solution Approach 1:
The patent extracts the common source region from under the isolation regions, confining it only to the active region between stacked gate structures. This extraction eliminates the corner rounding effects that occur when the source region extends under isolation regions, thereby maintaining low channel resistance while still achieving compact cell size through optimized source region placement.
Solution Approach 2:
The patent applies different spatial configurations to the common source region - it is present and continuous in the active region between gates where low resistance is needed, and absent under isolation regions where it would cause corner rounding. This local differentiation optimizes both electrical performance and cell dimensions.
3Productivity
If cell dimensions are reduced for downscaling, then memory density is improved, but corner rounding effects pinch off the channel
Solution Approach 1:
The patent transitions from a planar common source region to a three-dimensional configuration where the source region is vertically positioned and laterally confined to the active region. This dimensional change allows the source region to maintain channel continuity even when cell dimensions are reduced for downscaling, as the source region does not extend under isolation regions where corner rounding would occur.
Data Source
AI summary
Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head.