Split-Gate Flash Cell Layout for Stronger Floating-Gate Coupling
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Solution Overview
Problem
As memory cells are scaled down, achieving desired capacitive coupling between the floating gate and the control gate while avoiding unwanted capacitive coupling with other gates becomes increasingly difficult, affecting performance.
Innovation Solution
The method involves forming a memory cell with a floating gate having a concave upper surface that terminates at a sharp edge, a word line gate with a notch facing the sharp edge of the floating gate, and a coupling gate with a lower surface matching the concave shape of the floating gate, all insulated by layers of uniform thickness to enhance capacitive coupling and reduce unwanted interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory cells are scaled down to reduce cell size, then device density increases, but capacitive coupling between floating gate and control gate deteriorates while unwanted capacitive coupling with other gates increases
Solution Approach 1:
The floating gate is formed with a concave upper surface instead of a planar surface. This curvature increases the surface area of the floating gate that faces the control gate, thereby enhancing the capacitive coupling between these two gates. The increased coupling strength compensates for the reduced physical dimensions of the scaled-down memory cell, maintaining reliable operation despite the smaller cell size.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structures by creating notches in the control gate and coupling gate that face the sharp edge of the floating gate. This three-dimensional configuration increases the effective overlapping area between gates in the vertical dimension, enhancing capacitive coupling without increasing the lateral footprint of the cell, thus maintaining high density while improving coupling.
2Volume of moving object
If memory cells are scaled down, then device density increases, but unwanted capacitive coupling with other gates increases
Solution Approach 1:
The control gate and coupling gate are designed with notches that are localized at specific positions to face the sharp edge of the floating gate. This localized geometric feature concentrates the desired capacitive coupling at the notch regions while minimizing unwanted coupling with adjacent gates. The notches create a selective coupling pattern that enhances interaction with the floating gate while reducing parasitic coupling to other structures.
3Reliability
If floating gate has larger surface area for better capacitive coupling, then coupling strength increases, but device area increases
Solution Approach 1:
The concave upper surface of the floating gate increases its effective surface area for capacitive coupling with the control gate without increasing the lateral footprint of the device. The curvature is achieved within the existing cell boundaries, allowing enhanced coupling strength while maintaining the same device area and density.
Solution Approach 2:
The patent utilizes the vertical dimension by creating notches in the control and coupling gates that extend downward to face the floating gate's sharp edge. This vertical arrangement increases the effective overlapping area for capacitive coupling without expanding the lateral device area, thus maintaining high device density while achieving strong coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves capacitive coupling between the floating and control gates, enhancing read, program, and erase operational performance while minimizing unwanted capacitive coupling, thus maintaining performance at reduced cell sizes.
Implementation Method 1
The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26
Implementation Method 2
electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling
Implementation Method 3
Some of the heated electrons are injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Data Source
AI summary
A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.