Split-Gate Flash Memory Leakage Reduction via Dual Gate Height Control
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Solution Overview
Problem
Shrinking the size of elements in a split-gate flash memory cell, such as the floating gate and source/drain regions, is challenging due to control and tolerance issues, leading to leakage problems when the working voltage is high.
Innovation Solution
The formation of shallow trench isolations (STIs) and precise control of word line cells, memory gates, and spacers using techniques like chemical vapor deposition (CVD) and anisotropic dry etching, along with the use of CMP processes to achieve controlled heights and angles, reduces the risk of leakage by maintaining adequate distance between contacts and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of elements in a split-gate flash memory cell is shrunk to increase integration, then device density improves, but control precision and manufacturing tolerance deteriorate leading to leakage problems
Solution Approach 1:
The patent divides the gate structure into two separate gates (first gate electrode and second gate electrode) positioned at different heights, allowing independent control and optimization of each gate's dimensions and electrical characteristics, thereby maintaining manufacturing precision while achieving higher integration
Solution Approach 2:
The patent introduces vertical dimensionality by forming gate electrodes at different heights (first gate at lower level, second gate at higher level), transforming a planar scaling problem into a three-dimensional structure that maintains control precision while increasing device density
2Power
If the working voltage is increased to maintain performance during scaling, then device performance is preserved, but leakage current increases due to reduced breakdown voltage
Solution Approach 1:
The patent changes the electrical parameters by introducing dual gate electrodes with different potentials, allowing independent optimization of voltage levels to maintain performance while controlling leakage through enhanced breakdown voltage characteristics of the multi-gate structure
3Ease of manufacture
If conventional fabrication processes are used for shrinking elements, then process simplicity is maintained, but manufacturing tolerance and element size control deteriorate
Solution Approach 1:
The patent applies preliminary patterning actions to define precise gate electrode positions and dimensions before subsequent fabrication steps, establishing tight manufacturing tolerances early in the process while maintaining overall fabrication simplicity through sequential straightforward operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the precise control of memory gate and spacer heights, reducing the risk of leakage and enabling the scaling down of flash memory structures while maintaining performance, thus addressing the challenge of miniaturization in semiconductor devices.
Implementation Method 1
chemical vapor deposition (CVD)
Implementation Method 2
anisotropic dry etching
Implementation Method 3
CMP processes
Data Source
AI summary
Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.