Split Gate Flash Memory Cell Ion Implantation for Channel Current
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Solution Overview
Problem
The channel inversion region between the select gate and the floating gate in split gate flash memory cells increases resistance and reduces channel current, leading to lower erase window reliability and increased erase-related failures as integration levels rise and operating voltages decrease.
Innovation Solution
A semiconductor structure with an ion implantation region of a different type than the substrate, formed under the isolation wall between the select gate and the floating gate, connects channel inversion layers to ensure continuity and improve channel current, comprising N-type arsenic implantation with specific depth and concentration control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick isolation layer is used between the select gate and floating gate to prevent reverse tunneling, then reliability is improved, but the channel inversion depletion region increases resistance and reduces channel current
Solution Approach 1:
The patent applies different doping types in different locations: the substrate is doped with one type (e.g., P-type) while the ion implantation region under the isolation wall is doped with the opposite type (e.g., N-type). This local quality differentiation allows the isolation wall to maintain its thickness for reliability while the oppositely doped region compensates for the depletion effect, reducing resistance and improving channel current.
2Productivity
If high-level integration is pursued to reduce cell size and operating voltage, then productivity is improved, but the channel current level decreases and the influence of the channel inversion depletion region increases
Solution Approach 1:
The patent anticipates the harmful effect of the channel inversion depletion region that becomes significant at higher integration levels and lower voltages. By pre-introducing the ion implantation region with opposite doping type before the depletion region forms during operation, the patent counteracts the anticipated resistance increase, allowing high-level integration to proceed without sacrificing channel current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly enhances channel current during erase states, improving yield and reliability while maintaining compatibility with existing manufacturing processes and avoiding additional costs or complexity.
Implementation Method 1
an ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate
Data Source
AI summary
The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.