Split-Gate Flash Memory Layout for Scalable Independent Erase
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Solution Overview
Problem
The complexity and difficulty in configuring and implementing split gate non-volatile flash memory cell architectures increase as critical dimensions shrink, and there is a need to improve performance and manufacturing reliability of virtual ground memory cells as they are scaled down in size.
Innovation Solution
A semiconductor device with a layout of memory cells featuring a continuous channel region shared by pairs of memory cells, each with separate floating gates and word line gates, and independent erase gates, connected by orthogonal control and erase gate lines, and alternating bit lines for improved scalability and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional split gate memory cell architecture is used with separate channel regions for each cell, then each memory cell can be independently controlled, but the device complexity and difficulty of implementation increase significantly
Solution Approach 1:
The patent merges two separate channel regions into a single shared channel region that is controlled by two word line gates (first and second word line gates) positioned at different locations along the channel. This consolidation reduces the number of discrete components while maintaining independent control capability through the dual gate structure, directly resolving the contradiction between independent control and architectural complexity.
Solution Approach 2:
The single shared channel region is segmented into two distinct control zones by positioning the first word line gate over a first portion of the channel and the second word line gate over a second portion. This segmentation allows independent voltage application to different channel sections, enabling separate control of paired memory cells while using a unified channel structure, thus reducing overall device complexity.
2Quantity of substance
If memory cell components are scaled down in size to increase density, then storage capacity improves, but manufacturing reliability deteriorates
Solution Approach 1:
Adjacent pairs of memory cells share a common channel region and common word line gate structures, reducing the number of discrete components that must be manufactured at scaled dimensions. This merging approach maintains high cell density while improving manufacturing reliability by reducing the total number of features that require precise fabrication at small critical dimensions.
3Ease of operation
If more electrodes and separate channel regions are used for each memory cell, then independent cell operation is achieved, but the array layout becomes overly complex
Solution Approach 1:
The shared channel region serves multiple functions: it acts as the conduction path for both memory cells in a pair, provides the substrate for both floating gate and oxide nitride oxide layers, and enables independent control through the dual word line gate configuration. This multi-functionality reduces the number of separate components needed, simplifying array layout while maintaining independent cell operation capability.
Data Source
AI summary
A semiconductor device with interleaved active and isolation regions extending in a first direction. Memory cells formed in the active regions each include first and second drain regions, first and second floating gates, word line gate, first and second control gates, and first and second erase gates. Each of the active regions includes a plurality of first drain contacts each electrically connected to one of the first drain regions in the active region, and a plurality of second drain contacts each electrically connected to one of the second drain regions in the active region. A plurality of first bit lines extend in the first direction and each is electrically connected to the first drain contacts in one of the active regions. A plurality of second bit lines extend in the first direction and each is electrically connected to the second drain contacts in two of the active regions.