Split-Gate Flash Cell Leakage Suppression via Biasing
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Solution Overview
Problem
As memory cells are scaled down in size, reduced cell current leads to read errors, and lowering the memory cell threshold voltage to increase current results in programming errors due to increased column leakage.
Innovation Solution
Applying a small positive voltage to unselected source lines and/or a small negative voltage to unselected word lines during the read operation suppresses sub-threshold leakage, reducing column leakage and improving read performance without altering the memory cell threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell threshold voltage is lowered to increase cell current, then read performance is improved, but column leakage increases causing programming errors
Solution Approach 1:
The patent applies voltage biasing to unselected word lines and source lines during read operations to suppress sub-threshold leakage. By dynamically adjusting the voltage parameters of unselected lines (applying negative voltage to unselected word lines and positive voltage to unselected source lines), the method reduces column leakage without requiring a change to the memory cell threshold voltage, thus resolving the contradiction between read performance and programming accuracy
Solution Approach 2:
The patent preemptively applies counter-voltages to unselected lines before read operations to prevent sub-threshold leakage from occurring. By applying negative voltage to unselected word lines and positive voltage to unselected source lines in advance, the method creates a protective bias condition that actively counteracts the tendency toward leakage, preventing programming errors before they can occur
2Area of moving object
If memory cells are scaled down in size, then device density is improved, but cell current is reduced leading to read errors
Solution Approach 1:
The patent compensates for reduced cell current in scaled-down memory cells by applying voltage biasing to unselected lines during read operations. This parameter adjustment suppresses sub-threshold leakage that becomes more significant in smaller cells, thereby maintaining read accuracy despite the reduced cell current inherent in scaled-down device dimensions
3Reliability
If sub-threshold leakage is suppressed by voltage biasing, then programming errors are reduced, but device complexity increases
Solution Approach 1:
The patent utilizes existing word lines and source lines to serve dual functions: their primary function for normal memory operations and an additional function for suppressing sub-threshold leakage during read operations. By making these existing structures multi-functional, the method achieves programming accuracy improvement without adding dedicated leakage suppression circuitry, thus minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces programming errors by minimizing column leakage, enhancing read performance and reliability in split-gate non-volatile memory cells.
Implementation Method 1
a floating gate disposed over and insulated from a first portion of the channel region
Implementation Method 2
During programming, the target memory cell is programmed through efficient hot-electron injection with the portion of the channel under the floating gate in inversion
Implementation Method 3
During erase, a voltage of 9-11 volts is applied to the erase gate 24, to cause electrons to tunnel from the floating gate 22 to the erase gate 24
Data Source
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AI summary
A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first (16) and second (14) regions with a channel region (18) therebetween, a floating gate (22) disposed over a first portion of the channel region, a select gate (20) disposed over a second portion of the channel region, a control gate (26) disposed over the floating gate, and an erase gate (24) disposed over the first region. The method includes placing a small positive voltage on the unselected source lines (16), and/or a small negative voltage on the unselected word lines (20) during the read operation to suppress subthreshold leakage and thereby improve read performance.