Split Gate Flash Memory Liner-Separated Spacers
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Solution Overview
Problem
The integration of flash memory cells with logic circuits in semiconductor manufacturing is hindered by contamination from self-aligned silicide layers during chemical-mechanical polishing, leading to reduced manufacturing yields and precision limitations in defining small features, resulting in suboptimal flash memory device performance.
Innovation Solution
The implementation of a split gate memory cell structure where the top surfaces of select and memory gates are covered by spacers to prevent silicide formation, allowing for self-aligned formation and precise definition of these gates, thereby avoiding contamination and enabling denser data storage with higher manufacturing yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned silicide layers are formed on gate structures during CMP processes, then electrical connection is improved, but metal ion contamination occurs that reduces manufacturing yields
Solution Approach 1:
The patent extracts the harmful silicide formation from the gate structure by selectively removing the ability to form silicide on the top surfaces of select and memory gates. This is achieved through a multi-patterning process that creates non-conformal spacer structures, effectively taking out the problematic silicide layer formation capability while preserving the beneficial electrical connection properties where needed.
Solution Approach 2:
The patent applies local quality by creating different surface properties at different locations. The top surfaces of select and memory gates are modified to be non-silicidable (covered by spacer material), while other areas maintain their original silicide-forming capability. This localized modification prevents contamination at critical areas while preserving electrical connection benefits elsewhere.
2Ease of manufacture
If conventional photo masks are used to define gate structures, then manufacturing process is simple, but precision is limited for small critical dimensions
Solution Approach 1:
The patent segments the gate definition process into multiple steps using different patterning techniques. Instead of relying on a single photo mask step, the process is divided into: 1) initial photo mask patterning, 2) spacer formation, 3) selective removal, and 4) final gate structure definition. This segmentation enables precise definition of small critical dimensions while maintaining overall process feasibility.
Solution Approach 2:
The patent transitions from two-dimensional photo mask patterning to three-dimensional spacer-based self-alignment. By forming spacers that extend vertically and using them as alignment references for subsequent etching steps, the process achieves higher precision in defining small features without proportionally increasing lithographic complexity.
Data Source
AI summary
Some embodiments of the present disclosure relate to a split gate memory cell which includes a select gate and a memory gate. The select gate has a planar upper surface disposed over a semiconductor substrate and is separated from the substrate by a gate dielectric layer. The memory gate has a planar upper surface arranged at one side of the select gate and is separated from the substrate by a charge trapping layer. The charge trapping layer extends under the memory gate. A first spacer is disposed above the memory gate and is separated from the memory gate by a first dielectric liner. The first dielectric liner extends upwardly along an upper sidewall of the charge trapping layer; and source/drain regions are disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate.