Self-Aligned Split Gate Flash Memory Cell Structure
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Solution Overview
Problem
Conventional split gate flash memory cell fabrication techniques face challenges such as difficulty in controlling the height of memory gates, residue left on sidewalls leading to potential leakage, and contamination during silicide formation, which affect the integration of embedded flash memory with logic circuits and the reliability of chip periphery.
Innovation Solution
A new split gate memory cell structure with symmetrically disposed memory gates and select gates of cuboid shape, featuring planar top surfaces and self-aligned spacers that prevent silicide formation, allowing for precise definition and closer packing of flash cells, thereby enhancing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used to form memory gates, then the manufacturing process can be completed, but the height of memory gates cannot be precisely controlled and residue is left on sidewalls
Solution Approach 1:
The patent applies preliminary action by forming spacers on the sidewalls of select gates before forming the memory gates. These spacers serve as pre-positioned structures that define the final memory gate height and prevent residue formation. The spacers are formed as a preliminary step that establishes precise dimensional boundaries for subsequent memory gate formation, eliminating the need for complex height control during the main fabrication process.
2Reliability
If silicide formation is performed on memory gates, then electrical conductivity is improved, but contamination occurs affecting chip periphery reliability
Solution Approach 1:
The patent applies segmentation by dividing the gate structures into distinct functional zones using spacers. The spacers create clear separation between the select gate regions (where silicide formation is desired for conductivity) and the memory gate regions (where silicide must be prevented to avoid contamination). This segmentation allows selective silicide formation on select gates while protecting memory gates through the spacer barrier, thereby achieving both electrical conductivity improvement and contamination prevention.
3Productivity
If memory gates are formed with non-planar surfaces, then fabrication can proceed, but leakage occurs and yield decreases
Solution Approach 1:
The patent applies self-service by designing a self-aligned spacer formation process where the spacers automatically position themselves relative to the select gates without requiring additional alignment steps. The spacers form conformally on the select gate sidewalls and naturally define the memory gate boundaries, ensuring planar surfaces that prevent leakage. This self-aligning mechanism maintains high fabrication throughput while eliminating the need for complex alignment procedures that could compromise surface planarity.
Data Source
AI summary
The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.