Split-Gate Flash Memory Cell With Varying Insulation Gate Oxides
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Solution Overview
Problem
Existing methods for forming split gate non-volatile memory cells lack effective control over the formation of various elements, leading to inefficiencies in the fabrication process and performance optimization.
Innovation Solution
A method involving the sequential deposition and etching of silicon dioxide, polysilicon, and nitride layers, along with precise implantation and oxidation processes, is used to form memory cells with three gates, allowing for independent optimization of erase efficiency and word line gate performance by creating sloped surfaces and sharp edges for improved control over threshold voltages and insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for forming split gate memory cells, then the process is simpler, but control over formation of various elements is poor leading to performance optimization issues
Solution Approach 1:
The gate structure is divided into multiple segments: a first gate electrode, a second gate electrode, and a third gate electrode, each independently controllable. This segmentation allows precise control over threshold voltages and formation characteristics of different memory cell elements, resolving the contradiction by enabling better manufacturing precision through structured division of the gate control function
Solution Approach 2:
Different insulation layers (tunnel insulation layer, charge trapping insulation layer, block insulation layer) are applied to different regions and depths of the memory cell structure. This local differentiation enables optimized control over charge storage and threshold voltage adjustment in specific areas, improving manufacturing precision without requiring uniformly complex fabrication processes throughout the entire device
2Area of moving object
If cell size is reduced for scaling, then device density increases, but control over threshold voltages and performance optimization becomes more difficult
Solution Approach 1:
The gate is segmented into three independently controllable electrodes, allowing threshold voltage adjustment through individual gate control even in scaled-down cells. This enables precise voltage control in smaller area cells by applying different voltages to each gate segment, resolving the contradiction between reduced cell size and maintained manufacturing precision
Solution Approach 2:
The memory cell structure utilizes vertical layering with multiple insulation layers (tunnel, charge trapping, and block layers) stacked in different depths. This three-dimensional arrangement allows independent optimization of charge storage and threshold voltage control in the vertical dimension, enabling small footprint cells to maintain precise voltage control through layered structural complexity rather than lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise control over the formation of split gate memory cells, enhancing erase efficiency and word line gate performance, allowing for scalable cell size reduction and improved current drive, while minimizing defects and optimizing insulation layers for better performance.
Implementation Method 1
sequential deposition and etching of silicon dioxide, polysilicon, and nitride layers
Implementation Method 2
sequential deposition and etching of silicon dioxide, polysilicon, and nitride layers
Implementation Method 3
sequential deposition and etching of silicon dioxide, polysilicon, and nitride layers
Implementation Method 4
sequential deposition and etching of silicon dioxide, polysilicon, and nitride layers
Implementation Method 5
precise implantation and oxidation processes
Data Source
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AI summary
A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.