Split Gate Flash Memory Cell Sharp Corner Profile
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Solution Overview
Problem
Split gate flash memory devices face inefficiencies in erasure processes due to low erasure efficiency and the likelihood of 'over erasure' when using Fowler-Nordheim tunneling methods.
Innovation Solution
A fabrication method for a split gate flash memory cell is developed, featuring a floating gate with a sharp corner profile created by forming a semiconductor substrate with specific layers and etching processes, resulting in a width difference between the floating gate and control gate, enhancing electron distribution and erasure efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Fowler-Nordheim tunneling is used for erasure from floating gate to erase gate, then erasure function is achieved, but erasure efficiency is low and over erasure occurs
Solution Approach 1:
The floating gate is designed with different widths at different locations (narrower at corners, wider in center) to create localized electric field enhancement at corner regions. This local geometric variation concentrates the electric field at specific points during erasure, enabling more efficient electron tunneling from the floating gate to the erase gate while maintaining control over the erasure process and preventing over-erasure.
Solution Approach 2:
The invention transitions from a uniform two-dimensional floating gate structure to a three-dimensional structure with varying cross-sectional dimensions. By creating a floating gate with different widths in the lateral direction (narrower corners versus wider center), the patent introduces dimensional variation that enables field enhancement and improves tunneling efficiency in specific regions without affecting the overall device architecture.
2Manufacturing precision
If conventional fabrication process is used, then manufacturing simplicity is maintained, but floating gate cannot achieve sharp corner profile
Solution Approach 1:
The floating gate formation process is segmented into multiple sequential steps: first forming a wide conductive layer, then depositing a narrower cap layer, and finally using the cap layer as a mask during etching. This segmentation allows the floating gate to inherit the sharp corner profile from the cap layer while maintaining the overall structural integrity and electrical functionality.
Solution Approach 2:
A cap layer is introduced as an intermediary element between the conductive layer and the etching process. This cap layer serves multiple functions: it defines the narrow corner profile of the floating gate, acts as an etch mask to protect the conductive layer, and can be selectively removed afterward. The cap layer mediates between the requirement for sharp corners and the need to maintain conductive material continuity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The sharp corner profile on the floating gate increases the surface area, leading to enhanced point discharge and improved erasure efficiency from the floating gate to the erase gate, reducing the risk of over erasure.
Implementation Method 1
The split gate flash memory can be erased by Fowler-Nordheim tunneling of electrons from its floating gate through the underlying gate oxide layer to the substrate region
Implementation Method 2
Point discharge is likely to occur as the sharp corner profile changes electron distribution thereon
Data Source
AI summary
A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.