Split-Gate Flash Memory Cell With Erase Gate
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Solution Overview
Problem
Conventional split gate non-volatile memory cells face challenges in scaling down due to complex manufacturing processes and high costs, particularly in advanced technology nodes, where cell size is large and process complexity hinders efficient miniaturization.
Innovation Solution
A new technique for forming three-gate memory cells on a semiconductor substrate, which includes forming a silicon dioxide layer, followed by a silicon nitride layer, and then using a series of masking and etching steps to create trenches and layers for the floating gate, word line gate, and erase gate, allowing for independent scaling of oxide thickness and self-aligned floating gate formation, enabling smaller cell sizes with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional split gate memory cell structures are used, then manufacturing process is relatively simple and cost is low, but cell size is large and scaling down is difficult
Solution Approach 1:
The patent divides the gate structure into multiple segments: a first gate electrode, a second gate electrode, and a third gate electrode, each performing distinct functions. This segmentation allows independent optimization of each gate's thickness and material properties, enabling better scaling while maintaining manufacturing feasibility. The floating gate is also segmented into portions that can be independently controlled by different gate electrodes.
Solution Approach 2:
The patent transitions from planar 2D scaling to 3D vertical stacking by introducing multiple gate electrodes at different heights and positions. The first gate electrode is disposed at a first height, the second gate electrode at a second height, and the third gate electrode at a third height, creating a three-dimensional gate structure that achieves higher integration density without proportionally increasing manufacturing complexity.
2Reliability
If four-gate memory cell structures are used, then erase tunneling performance is improved, but process complexity and cost increase
Solution Approach 1:
The patent makes the third gate electrode serve multiple functions: it acts as an erase gate for electron removal from the floating gate, and simultaneously serves as a control gate for reading operations and as a select gate for programming operations. This multi-functionality achieves the erase performance benefits of a dedicated erase gate while reducing the total number of separate gate structures needed.
Solution Approach 2:
The patent combines the functions of what would traditionally require separate erase gate, control gate, and select gate structures into a unified three-electrode configuration. The third gate electrode integrates multiple gate functions, and the shared polysilicon layer unifies the word line and logic gate structures, thereby reducing process complexity while maintaining erase tunneling performance.
3Area of moving object
If oxide thickness is scaled down for smaller cells, then cell size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different oxide thicknesses to different regions and functions: a first oxide layer with a first thickness for the tunneling region, a second oxide layer with a second thickness for the control region, and a third oxide layer with a third thickness for the erasure region. This local differentiation allows optimized thickness for each function while maintaining overall manufacturability.
Solution Approach 2:
The patent independently varies oxide thickness parameters across different regions and layers. By changing the thickness parameter locally rather than uniformly, the patent achieves better control over electron tunneling characteristics in each region while relaxing the overall manufacturing precision requirements compared to uniform thin-oxide scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, allows for reliable scaling down of memory device size, and enhances erase tunneling performance by using a separate erase gate and shared polysilicon layer for word line and logic gates, improving endurance and reducing operational voltages.
Implementation Method 1
forming a silicon dioxide layer, followed by a silicon nitride layer
Implementation Method 2
using a series of masking and etching steps to create trenches and layers for the floating gate, word line gate, and erase gate
Implementation Method 3
The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26
Implementation Method 4
electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling
Implementation Method 5
Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Data Source
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AI summary
A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.