Split-Gate Flash Memory Cell Erase Gate Programming
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Solution Overview
Problem
Hot-electron injection programming for split gate memory cells requires high electrical current and is inefficient, making mass programming difficult and time-consuming due to the need for large voltage and current sources and low electron injection efficiency.
Innovation Solution
A memory device with a semiconductor substrate and control circuitry that uses an erase gate to apply a negative voltage for programming and a positive voltage for erasing, significantly reducing the electrical current required and increasing efficiency by ensuring nearly all electrons tunnel to the floating gate, allowing for simultaneous programming of multiple cells with reduced hardware needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hot-electron injection programming is used for split gate memory cells, then programming capability is achieved, but high electrical current is required and programming efficiency is low
Solution Approach 1:
The patent replaces the hot-electron injection mechanism (which relies on electron heating and acceleration through the channel) with direct electron tunneling from the erase gate to the floating gate. This substitution eliminates the need for high current flow through the channel and associated heating processes, directly achieving electron transfer through quantum tunneling when the erase gate is at a higher potential than the floating gate.
Solution Approach 2:
The patent introduces an erase gate as an intermediary structure between the control gate and the floating gate. This erase gate serves as a direct electron source that can tunnel electrons onto the floating gate without requiring high current through the channel, thereby mediating the programming process to achieve low-current operation.
2Productivity
If hot-electron injection programming is used, then programming capability is achieved, but mass programming becomes difficult and time-consuming
Solution Approach 1:
The patent replaces the complex hot-electron injection system (requiring high voltage sources, current sources, and precise timing control) with a simpler direct tunneling system. The erase gate can be driven by a single voltage source that raises its potential above the floating gate, eliminating the need for complex current sourcing and timing synchronization required for hot-electron injection.
Solution Approach 2:
The erase gate serves multiple functions: it acts as an electron source for programming, and when reversed in polarity, can serve as an electron sink for erase operations. This multi-functionality simplifies the overall device architecture and control circuitry compared to separate programming and erase mechanisms.
3Productivity
If hot-electron injection is used for programming, then electrons are injected onto the floating gate, but electron injection efficiency is low
Solution Approach 1:
The patent replaces the inefficient hot-electron injection process (where only a small fraction of electrons gain sufficient energy to overcome the oxide barrier) with direct quantum tunneling. In the tunneling mechanism, electrons directly tunnel from the erase gate through the oxide to the floating gate when the erase gate potential exceeds the floating gate potential, achieving near 100% electron transfer efficiency without energy loss from ineffective heating and acceleration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The erase gate programming technique reduces the electrical current needed for programming, enabling faster and more efficient programming of split gate memory cells with lower hardware requirements, improving scalability and reducing the size and cost of memory devices.
Implementation Method 1
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via the well-known technique of Fowler-Nordheim tunneling.
Implementation Method 2
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via the well-known technique of Fowler-Nordheim tunneling.
Implementation Method 3
The portion of the channel region 18 under the control gate 22 is turned on (made conductive) by the positive voltage on the control gate 22. The portion of the channel region 18 under the floating gate 20 is turned on (made conductive) by the positive voltages on the control gate 22 and drain region 16 being capacitively coupled to the floating gate 20. Electron current will flow starting from the source 14 towards the drain 16 in the portion of the channel region 18 under the control gate 22. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 and onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. This programming technique is well known as hot-electron injection
Data Source
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AI summary
A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.