Split Gate Flash Memory Erasing Gate Structure
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Solution Overview
Problem
There is a need to improve the performance of split gate flash memory, particularly in terms of erasing and writing efficiency, as existing technologies face challenges with over erasure and coupling voltage issues.
Innovation Solution
A method for forming a memory structure involving a base with fins, where a floating gate structure is formed across the floating gate region, surrounded by a sacrificial layer, and an erasing gate structure is created with a planar surface, optimizing the coupling area between the floating gate and source while minimizing the coupling area with the erasing gate to enhance programming and erasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked flash memory structure with floating gate and control gate is used, then integration and storage speed are improved, but over erasure problem occurs
Solution Approach 1:
The gate structure is segmented into separate control gate and erasing gate components positioned at different locations. The control gate is disposed at a first location above the channel, while the erasing gate is disposed at a second location adjacent to the channel, allowing independent control of programming and erasing operations to prevent over erasure while maintaining high storage speed.
2Reliability
If conventional split gate flash memory is used, then over erasure is avoided, but programming and erasing efficiency needs improvement
Solution Approach 1:
Different gate structures are implemented at different locations: a control gate at the first location for programming operations and an erasing gate at the second location for erasing operations. This local differentiation optimizes each operation's efficiency while maintaining the reliability benefits of split gate architecture.
Solution Approach 2:
The erasing gate is positioned adjacent to the channel in a lateral dimension rather than only vertically above it. This dimensional change creates a planar erasing gate structure that enhances coupling area and improves erasing efficiency while avoiding over erasure problems.
3Productivity
If coupling area between floating gate and source is increased, then programming efficiency is improved, but device area increases
Solution Approach 1:
The floating gate structure extends laterally adjacent to the source region in addition to being positioned above it. This dimensional extension increases the coupling area between floating gate and source for improved programming efficiency without requiring a proportional increase in vertical device area.
Data Source
AI summary
The present disclosure provides a memory and a method for forming the memory. The method includes: providing a base with a first fin and a second fin formed thereon, wherein the first fin comprises an erasing region and a floating gate region on both sides of the erasing region, and a sacrificial layer is disposed on a surface of the erasing region and a surface of the second fin; forming a floating gate structure across the floating gate region on the base; forming a first sidewall film on a top surface and sidewall surfaces of the floating gate structure on the base; removing the sacrificial layer, and forming an opening in the floating gate structure and the first sidewall film; and forming an erasing gate structure in the opening. The memory formed by the method has good performance.