Split Gate Flash Memory Integration with Logic Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices face challenges in optimizing the integration of memory cells with processing circuitry on a single chip, particularly in reducing power consumption and package size while maintaining high processing speed and cost-effectiveness.
Innovation Solution
The integration of split gate flash memory cells on a recessed substrate with specific bias conditions and dielectric structures, including floating gate, control gate, and select gate electrodes, allows for efficient data storage and retrieval, enabling the formation of a compact and efficient memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory is manufactured on a dedicated microchip coupled with processor circuits in separate packages, then manufacturing precision and reliability are improved, but device complexity and package size increase
Solution Approach 1:
The patent combines the flash memory array and processor circuits into a single integrated chip structure. The memory device includes memory cells formed over a substrate with control gates, floating gates, and source/drain regions, alongside integrated logic circuits that share common substrates and interconnect structures. This merging eliminates the need for separate packages and coupling interfaces, reducing device complexity while maintaining reliability through unified manufacturing processes.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it supports both the memory cell structures (as the base for wells, gates, and electrodes) and the logic circuit components. The interconnect layers and vias provide universal electrical pathways that connect both memory arrays and processing elements. This multi-functionality reduces the overall package structure complexity while maintaining reliable electrical connections between all components.
2Speed
If flash memory array is integrated with logic and control circuitry on a single chip, then processing speed and power consumption are improved, but manufacturing precision requirements increase
Solution Approach 1:
The integrated chip is segmented into distinct functional regions: memory cell arrays with their specific gate structures, logic circuit blocks with transistors and interconnects, and dedicated interconnect regions. Each segment is optimized for its specific function while sharing common substrate and manufacturing processes. The memory cells include segmented control gates (first and second control gates) and floating gates that can be independently configured, allowing precise control over memory operations without affecting the entire chip.
Solution Approach 2:
Different regions of the chip have locally optimized structures: memory regions feature thick dielectric layers and specific gate configurations for data storage, while logic regions have optimized transistor geometries and interconnect densities for processing. The interconnect structures vary locally to match the requirements of adjacent functional blocks. This local quality approach allows high-speed operation in logic regions while maintaining reliable data storage in memory regions, all achieved through standard semiconductor manufacturing processes.
3Ease of manufacture
If separate packages are used for memory chip and processor circuits, then manufacturing cost is reduced, but package size and power consumption increase
Solution Approach 1:
The patent merges the memory array and logic circuits onto a single integrated chip, eliminating the need for multiple separate packages and their associated packaging materials, bonding wires, and mounting structures. This consolidation reduces the overall package size while maintaining cost-effectiveness through unified manufacturing processes that leverage standard semiconductor fabrication techniques for both memory and logic components on the same substrate.
Data Source
AI summary
A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.