Split-Gate Flash Memory Cell With Sloping Floating Gate
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Solution Overview
Problem
The scaling down of split-gate flash memory cells is hindered by reduced capacitive coupling between the floating and control gates due to smaller substrate sizes, and the quality of the tunnel oxide is difficult to control, especially with advanced technology nodes.
Innovation Solution
The configuration includes a floating gate with a sloping upper surface and sharp edges, an erase gate formed vertically over the floating gate, and a control gate laterally adjacent to the floating gate, enhancing capacitive coupling and protecting the tunnel oxide from subsequent processing, allowing for reduced erase gate dimensions and improved erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the critical dimension of the control gate is shrunk to reduce memory cell size, then the memory cell area is reduced, but the capacitive coupling between the floating gate and control gate is reduced
Solution Approach 1:
The patent introduces a vertically-oriented floating gate with a sloping upper surface, transitioning from a conventional horizontal gate structure. This vertical configuration increases the surface area of the floating gate that is laterally adjacent to the control gate, thereby enhancing capacitive coupling without increasing the lateral footprint of the memory cell. The sloping surface creates additional coupling area while maintaining compact lateral dimensions.
Solution Approach 2:
The patent employs a composite gate structure where the floating gate is formed with a sloping upper surface that includes both vertical and inclined portions. This composite geometry allows the floating gate to maximize its lateral adjacency with the control gate within the constrained lateral space, improving capacitive coupling while maintaining small memory cell area.
2Adaptability or versatility
If the tunnel oxide is exposed to subsequent logic oxide nitridation or HKMG processing, then advanced technology node processing is enabled, but the quality of the tunnel oxide becomes difficult to control
Solution Approach 1:
The patent applies a protective capping layer over the tunnel oxide and floating gate structure before subsequent processing steps. This protective layer prevents the tunnel oxide from being exposed to harmful processing conditions such as oxide nitridation and HKMG processing, thereby preserving tunnel oxide quality while still enabling compatibility with advanced technology node manufacturing processes.
Solution Approach 2:
The patent introduces a protective capping layer as an intermediary between the tunnel oxide and subsequent processing steps. This intermediary layer acts as a barrier that protects the sensitive tunnel oxide from degradation during logic oxide nitridation and HKMG processing, allowing advanced technology node processing to proceed without compromising tunnel oxide quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances capacitive coupling between the control and floating gates, enables efficient scaling of memory cells, and protects the tunnel oxide quality, thereby improving programming and erase performance without increasing the lateral footprint of the floating and erase gates.
Implementation Method 1
Capacitive coupling between the control gate 18 and the floating gate 10 during operation is achieved by forming the control gate 18 over the floating gate 10
Implementation Method 2
the tunnel oxide between the floating gate 10 and the erase gate 20 (through which electrons tunnel during an erase operation)
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
A non- volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate there between. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.