Split Gate Flash Memory Metal Trace for Plasma Stress Relief
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Solution Overview
Problem
The stress on semiconductor devices due to large potential differences during manufacturing processes, such as plasma dry etch, ion implant, or plasma enhanced CVD, degrades their performance, endurance, and reliability in split-gate charge trapping memory cells and field-effect transistors.
Innovation Solution
A semiconductor device and method that includes a split-gate memory cell with a first and second gate, doped regions, and p-n junctions, where a metal trace connects the second gate of a memory cell to a p-n junction, using vias and conductive material to form electrical connections, thereby reducing stress and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high drain and gate voltages are used for programming, then hot carrier injection efficiency is improved, but current consumption increases
Solution Approach 1:
The gate is divided into two separate gates: a select gate and a memory gate. During programming, the select gate is biased at a relatively low voltage while only the memory gate is biased at high voltage. This segmentation allows the high voltage to be applied only where needed (under the memory gate) for efficient hot-carrier injection, while the select gate operates at lower voltage to reduce overall current consumption.
2Ease of manufacture
If large potential difference is applied during manufacturing processes, then device fabrication is enabled, but device stress and reliability degrade
Solution Approach 1:
A metal trace is provided that electrically connects the memory gate to a p-n junction, enabling the memory gate to be discharged to ground potential before and during manufacturing processes such as plasma dry etch, ion implant, or plasma enhanced CVD. This preliminary discharge action prevents large potential differences from developing, thereby avoiding stress-induced degradation and reliability issues while still allowing these manufacturing processes to be performed.
Data Source
AI summary
A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.