Split Gate Flash Memory for Neuromorphic Processing
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Solution Overview
Problem
Current NN systems face challenges in efficient training and classification due to limitations in split gate flash MLC based neuromorphic processing.
Innovation Solution
The integration of MLC split-gate flash memory with artificial neuromorphic processing, allowing for dynamic programming and erasing of each cell, and the use of convolutional neural networks for sensing and classifying visual imagery, enabling classification with analog memory and adder circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MLC technology is used to increase cell density, then manufacturing costs are reduced, but the complexity of programming and erasing operations increases
Solution Approach 1:
The gate is divided into two separate gates (first gate and second gate) that can be independently controlled. This segmentation allows selective programming of individual cells within a block without affecting other cells, simplifying the overall programming operation despite the multi-level complexity
2Ease of manufacture
If feature size is scaled down to increase density, then manufacturing costs are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The memory array is divided into multiple blocks, each containing cells that can be independently programmed and erased. This block-level segmentation allows for more relaxed precision requirements in individual manufacturing steps while still achieving high overall density through the scaled feature sizes
3Adaptability or versatility
If MLC split-gate flash memory is used for neuromorphic processing, then training and classification capabilities are enhanced, but the device complexity increases
Solution Approach 1:
The split-gate flash memory cell is designed to serve multiple functions: it can store data traditionally, perform neuromorphic processing for training neural networks, and execute classification tasks. This multi-functionality is achieved through the dual-gate structure that enables both conventional flash operations and analog-weight adjustment for neuromorphic applications
Solution Approach 2:
The device incorporates dynamic control capabilities where the first and second gates can be independently biased to dynamically adjust the threshold voltage of memory cells. This dynamic adjustment enables the cells to function as adjustable synapses in neuromorphic networks, providing adaptability for learning and classification while maintaining a relatively simple physical structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the training and classification capabilities of NN systems, achieving efficient and accurate processing with increased density and reduced manufacturing costs, applicable in various semiconductor devices.
Implementation Method 1
A self-aligned split gate flash cell integrated in a logic process of integrated circuits is erased via poly-to-poly Fowler-Norheim (FN) tunneling across a filed-enhanced asymmetric tunneling barrier formed between a floating gate (FG) and an erase gate (EG)
Implementation Method 2
The programming mechanisms of these flash memory devices can include charge carrier paths between the floating gate and drain or alternatively between the floating gate and source via hot carrier injection or FN tunneling
Data Source
AI summary
The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.