Split Gate Flash Memory Scaling via Ion Implantation
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Solution Overview
Problem
Conventional flash memory devices face challenges in scaling down due to the thinning of control gates, which can lead to ion implantation penetration and failure of memory gates, making it difficult to further reduce device size for increased packing density and cost efficiency.
Innovation Solution
A method and device are developed to fabricate a flash memory structure by forming a memory gate and control gate using a polysilicon layer, with an oxide-nitride-oxide layer and ion implantation processes to create source and drain regions, allowing for the formation of a split gate SONOS flash memory device that can withstand size scaling by modifying the memory gate shape and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the control gate is scaled down to reduce device size, then packing density and cost efficiency are improved, but the memory gate thickness becomes too thin causing ion implantation penetration and device failure
Solution Approach 1:
The gate structure is divided into two separate gates: a control gate and a memory gate. This segmentation allows each gate to be independently optimized - the control gate can be made thicker to prevent ion implantation penetration while the overall device size is reduced through efficient spatial arrangement of the split gate structure
Solution Approach 2:
The patent transitions from a conventional single planar gate to a three-dimensional split gate structure where the control gate and memory gate are positioned at different spatial locations and orientations. This dimensional change enables independent thickness control of each gate component, resolving the contradiction between size scaling and memory gate integrity
2Length of moving object
If the control gate thickness is reduced to enable further scaling, then device size is reduced, but ion implantation penetrates through the thin gate causing device failure
Solution Approach 1:
By separating the gate into control gate and memory gate components, the patent allows the memory gate to be positioned and dimensioned specifically to block ion implantation paths, while the control gate can be optimized for electrical control functions. This segmentation enables the memory gate to serve as a protective barrier against ion penetration
Solution Approach 2:
The memory gate acts as an intermediary barrier between the ion implantation source and the sensitive channel region. By positioning the memory gate in this intermediate location, it intercepts and blocks harmful ion implantation while allowing the control gate to perform its electrical control function at a different location
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method enables the fabrication of a flash memory device that can scale down in size effectively, maintaining the functionality of memory gates by altering the memory gate shape and structure, thus addressing the limitations of conventional scaling methods.
Implementation Method 1
performing an ion implantation process to form a source and a drain in the wafer substrate
Data Source
AI summary
The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.