Split Gate Flash Memory Select Gate Damage Prevention

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Solution Overview

Problem

Existing methods for forming SONOS or MONOS split gate flash memory cells damage select gates and gate dielectrics due to the reduction in thickness of the charge trapping dielectric layer within the central region, leading to sidewall damage, especially in 28 nm micro fabrications.

Innovation Solution

The method involves forming a charge trapping dielectric layer that does not line the central region between the select gates, using a dielectric liner and a sacrificial spacer to fill the central region, preventing damage to the select gates and gate dielectrics during the removal of exposed portions of the charge trapping dielectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the charge trapping dielectric layer is formed to line the central region between select gates, then the memory cell structure is complete, but the select gates and gate dielectrics suffer sidewall damage during subsequent processing

Engineering Contradiction:

Improveintegrity of select gate sidewallsVSAvoidsidewall damage to select gates

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A dielectric liner is introduced as an intermediary layer between the charge trapping dielectric and the select gates. This liner prevents direct contact and potential damage to the select gate sidewalls during charge trapping dielectric formation and subsequent processing steps, while still allowing the memory cell structure to function properly.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric liner is formed in advance, before the charge trapping dielectric is deposited. This preliminary action ensures that the protective barrier is already in place to prevent sidewall damage during the subsequent charge trapping dielectric formation and etching processes.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If conventional methods are used to form charge trapping dielectric in the central region, then the dielectric layer is continuous, but process window is reduced and damage occurs at 28 nm fabrication node

Engineering Contradiction:

Improveprocess windowVSAvoiddamage-free fabrication at 28 nm

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The dielectric liner serves as a protective intermediary that enables reliable fabrication at the 28 nm node by preventing damage to critical structures during charge trapping dielectric processing, thereby expanding the process window for manufacturing.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9502515B2Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure

Publication Date: 2016.11.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.