Split-Gate Flash Cell Source Driver Mitigates Program Gate Disturb
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Solution Overview
Problem
Split-gate flash cell arrays face high voltages being applied to unselected memory cells, leading to undesirable 'program gate disturb' due to the coupling of control gates during various memory operations, which increases manufacturing costs and reduces efficiency.
Innovation Solution
Implementing a source driver circuitry that floats the sources of unselected memory cells during programming operations, thereby preventing the application of unnecessary voltage and reducing gate disturb without re-engineering the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to control gates during programming operations, then programming effectiveness is improved, but program gate disturb in unselected memory cells increases
Solution Approach 1:
The patent applies different voltage conditions to different regions of the memory array by selectively controlling source voltages. Selected memory cells receive appropriate programming voltages while unselected cells have their sources floated to prevent voltage application, creating localized quality differences that resolve the contradiction between programming effectiveness and gate disturb.
Solution Approach 2:
The source driver circuitry acts as an intermediary element that controls the source voltage of memory cells. By inserting this control mechanism between the programming operation and the memory cells, it enables selective voltage application - allowing high voltage to selected cells for effective programming while preventing voltage application to unselected cells, thus reducing program gate disturb.
2Adaptability or versatility
If control gate driver applies voltage to all control gates, then operation coverage is improved, but unnecessary voltage application to unselected cells increases
Solution Approach 1:
The patent implements local quality control by making the source voltage condition dependent on selection status. Selected memory cells receive floating source conditions that enable voltage application, while unselected cells have sources connected to ground, creating localized differences in voltage reception that reduce energy waste while maintaining operation coverage.
Solution Approach 2:
The source driver circuitry dynamically adjusts source voltages based on real-time selection status. During programming operations, sources of selected cells are floated to enable voltage application, while sources of unselected cells are grounded to prevent voltage application. This dynamic adaptation allows the system to maintain operation coverage while minimizing unnecessary energy consumption.
3Ease of operation
If sources of unselected memory cells are kept at ground potential, then control is simplified, but gate disturb mitigation is reduced
Solution Approach 1:
The patent employs dynamic control of source voltages rather than static grounding. The source driver circuitry switches between two states: floating the source during programming operations to mitigate gate disturb, and grounding during other operations for simplicity. This dynamic approach resolves the contradiction by adapting the control method to the specific operation being performed.
Solution Approach 2:
The source voltage control operates periodically based on operation type - floating during programming operations to reduce gate disturb, and grounding during read or idle operations for control simplicity. This periodic switching between control modes allows the system to optimize for gate disturb mitigation when needed while maintaining ease of operation during other phases.
Data Source
AI summary
A memory circuit has control gate circuitry (104) and select gate circuitry (106). A first memory cell (122/124) has a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a first bit line for reading a logic state of the of the first memory cell, and a source. A second memory cell (150/152 or 158/160) having a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a second bit line for reading a logic state of the of the second memory cell, and a source. A source control circuit (102) that, during programming of the first memory cell, outputs a first voltage to the source of the first memory cell and keeps the source of the second memory cell floating.