Split-Gate Flash Memory Spacer Reduces Gate Interference
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Solution Overview
Problem
Conventional split-gate flash memory devices face issues with read disturbance, program disturbance, and sidewall scaling limitations, which affect packing density and interference between the word gate and the floating gate.
Innovation Solution
A dielectric spacer comprising a low-k layer and a first high-k layer is provided between the word gate and the memory gate stack, with optional additional high-k layers and work function tuning layers to reduce interference and enable further sidewall scaling, and the spacer can be replaced with an air gap to minimize leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of spacer is increased to prevent read/program disturbance, then interference between word gate and floating gate is reduced, but packing density is adversely impacted and sidewall scaling is restricted
Solution Approach 1:
The spacer is constructed as a composite structure with a first dielectric material (lower dielectric constant) and a second dielectric material (higher dielectric constant). This composite configuration allows optimization of both interference prevention and packing density by leveraging the complementary properties of different dielectric materials - the lower-k material reduces capacitive coupling while the higher-k material maintains electrical characteristics
Solution Approach 2:
Different portions of the spacer structure are assigned different dielectric materials based on local functional requirements. The first dielectric material is positioned in regions where interference reduction is critical, while the second dielectric material is placed where electrical coupling is needed, creating spatially varying properties that simultaneously address both contradictions
2Reliability
If the width of spacer is increased to prevent read/program disturbance, then charge transfer between gates is reduced, but sidewall scaling is restricted
Solution Approach 1:
The multi-material spacer enables prevention of charge transfer without increasing overall spacer width. The composite structure achieves interference prevention through optimized dielectric property distribution rather than dimensional increase, thereby preserving sidewall scaling capability
Solution Approach 2:
Instead of changing the geometric parameter (spacer width), the invention changes the material parameters (dielectric constants) to achieve the same functional outcome of preventing charge transfer, thus maintaining scalable dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer dielectric spacer reduces read and program disturbances, allows for improved sidewall scaling, and decreases series resistance by enhancing coupling to the channel, while the air gap minimizes charge transfer, thereby reducing interference and maintaining device performance.
Implementation Method 1
providing a dielectric spacer between the word gate and the memory gate stack, the dielectric spacer comprising a low-k layer and a first high-k layer
Implementation Method 2
the spacer can be replaced with an air gap to minimize leakage paths
Data Source
AI summary
A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.