Split Gate Flash Memory Cells With Trench-Formed Select Gate
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Solution Overview
Problem
Current split gate flash memory cell designs require complex processes and additional components, such as a control gate, which can increase the size and complexity of the device, and do not efficiently improve data erase times.
Innovation Solution
A structure and method for a split gate flash memory cell that includes a semiconductor substrate with a trench, source/drain regions, a first gate laterally positioned between the trench and the second source/drain region, and a second gate with a portion inside the trench, where a dielectric layer is positioned between the second gate and the substrate, simplifying the formation process and reducing the need for additional polishing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a control gate is added to improve data erase times, then erase speed is improved, but device complexity and size increase
Solution Approach 1:
The patent combines the control gate and select gate functions into a single gate structure, eliminating the need for a separate control gate while maintaining efficient erase performance. The gate is positioned to simultaneously serve as both control and select gate, reducing device complexity without sacrificing erase speed.
Solution Approach 2:
The single gate structure performs multiple functions: it acts as both the control gate for charge transfer during erase operations and the select gate for channel control. This multi-functionality eliminates redundant components while preserving the improved erase times achieved by split gate architectures.
2Manufacturing precision
If additional polishing steps are added to form the gate structure, then manufacturing precision is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure extends into the trench vertically, utilizing the third dimension to achieve proper gate positioning and control. This vertical extension eliminates the need for additional polishing steps to achieve the required gate geometry, as the trench depth provides the necessary dimensional control.
Solution Approach 2:
The trench is formed beforehand in the substrate, providing a pre-defined cavity that guides subsequent gate formation. This preliminary trench creation establishes the gate's vertical position and dimensions before gate material deposition, eliminating the need for post-formation polishing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size of the memory cell, increases device density, and simplifies the construction by eliminating the need for a separate erase gate, while improving data erase times through efficient charge transfer mechanisms.
Implementation Method 1
A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate
Data Source
AI summary
Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.