Split-Gate GaN Power Transistor for Light-Load Efficiency
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Solution Overview
Problem
Current power converters face efficiency compromises at light load conditions, where existing GaN power transistors fail to maintain high efficiency due to trade-offs between efficiency and power density, leading to increased semiconductor losses and reduced performance.
Innovation Solution
A configurable multi-terminal GaN power transistor with a split-gate design allows for dynamic tuning of figures of merit during operation by modifying the die area and capacitances, enabling optimal performance across light and heavy load conditions through separate gate, source, and drain terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-terminal GaN power transistor is used, then the device structure is simple, but the efficiency at light load conditions deteriorates due to fixed figures of merit that cannot be optimized for varying load conditions
Solution Approach 1:
The GaN power transistor is divided into multiple independent unit cells (first plurality and second plurality), each with its own gate terminal. This segmentation allows different portions of the device to be independently controlled, enabling optimization of figures of merit for different load conditions while maintaining a relatively simple overall device structure.
Solution Approach 2:
The device incorporates multiple gate terminals that allow dynamic reconfiguration of the active device area during operation. By selectively activating different unit cells based on load conditions, the figures of merit (input capacitance, output capacitance, on-resistance) can be dynamically adjusted to minimize semiconductor losses across varying operating conditions.
2Ease of manufacture
If a fixed device configuration is used, then manufacturing is simple, but adaptability to different load conditions deteriorates
Solution Approach 1:
The device is manufactured as an integrated structure with multiple unit cells and gate terminals, maintaining relatively simple fabrication processes. The segmented design is built into the device architecture during manufacturing, enabling post-fabrication adaptability to different load conditions without requiring complex assembly or modification steps.
Solution Approach 2:
The multi-terminal GaN power transistor is designed as a universal device that can operate in multiple configurations to handle different load conditions. The same physical device structure serves multiple functions by selectively activating different unit cells, providing adaptability to various operating conditions without requiring multiple specialized devices.
Data Source
AI summary
The present disclosure relates to a Gallium Nitride (GaN) power transistor. The GaN power transistor includes a source pad, a drain pad, a first and a second gate pad, a plurality of unit cells where each unit cell includes a source region, a drain region and a gate region. The power transitory further includes a source metallization layer contacting the source regions of the plurality of unit cells with the source pad, a drain metallization layer contacting the drain regions of the plurality of unit cells with the drain pad, a first gate metallization layer contacting the gate region of a first portion of the unit cells with the first gate pad, and a second gate metallization layer contacting the gate region of a second portion of the unit cells with the second gate pad.