Split Gate Inter-Poly Oxide Layer Etch Control
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Solution Overview
Problem
Conventional manufacturing processes for semiconductor power devices with split trenched-gate structures face challenges such as high gate-to-drain capacitance, premature breakdown due to weak gate oxide, and compromised performance from over-etching during wet etch processes, especially as cell density increases and trench dimensions shrink.
Innovation Solution
The implementation of a high-density plasma (HDP) deposition process for forming the inter-poly oxide layer, followed by annealing and controlled etching to achieve a uniform and thicker inter-poly insulation layer, which prevents over-etching and enhances the planar surface characteristics, thereby reducing gate-to-drain capacitance and improving device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional wet etch process is used to remove sidewall oxide, then the oxide can be removed, but over-etching occurs creating pockets that cause early breakdown and compromise device performance
Solution Approach 1:
The patent changes the etch process parameters by using a buffered HF etch with controlled concentration and timing, followed by a dip in deionized water to stop the etch precisely at the desired depth, preventing over-etching and pocket formation while still effectively removing damaged oxide
Solution Approach 2:
The patent applies a preliminary rinse in deionized water immediately after the HF etch to neutralize and stop the etching action before it can create over-etching pockets, preventing the harmful effect before it occurs
2Object-generated harmful factors
If the inter-poly oxide layer is made thinner to reduce capacitance, then gate-to-drain capacitance decreases, but the oxide becomes weaker and prone to breakdown
Solution Approach 1:
The patent optimizes the inter-poly oxide thickness parameter to a specific range (50-200 nm) that balances capacitance reduction with sufficient mechanical and electrical strength to prevent breakdown, and uses controlled etching to achieve uniform thickness without creating weak spots
3Productivity
If the trench dimensions are reduced to increase cell density, then device integration increases, but the gate oxide becomes more vulnerable to over-etching and breakdown
Solution Approach 1:
The patent adjusts the etch process parameters including HF concentration, etch time, and rinse conditions to achieve uniform etching across smaller trench dimensions, preventing non-uniform pocket formation that would be more critical in high-density configurations
Solution Approach 2:
The patent applies preliminary controlled etching with immediate neutralization to prevent pocket formation before it can occur, which is especially important for maintaining etch uniformity in smaller, higher-density trenches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate-to-drain capacitance, enhances the breakdown voltage, and improves the overall performance and reliability of semiconductor power devices by maintaining the integrity of the gate oxide and controlling the inter-poly oxide thickness, leading to increased device ruggedness and efficiency.
Implementation Method 1
The inter-poly oxide layer is formed by a high-density plasma (HDP) deposition process
Implementation Method 2
The HDP oxide is annealed to increase its etch rate to substantially the same as an etch rate of a thermal oxide
Data Source
AI summary
This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.