Split-Gate Lateral Extended Drain MOS Transistor Structure
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Solution Overview
Problem
Operating lateral drain extended MOS transistors at higher frequencies is limited by gate-drain capacitance and achieving desired resistances for improved power efficiency has been problematic.
Innovation Solution
A split-gate lateral extended drain MOS transistor design with a first gate and a second gate separated by a gap of 10 nanometers to 250 nanometers, where the second gate provides a constant on-state gate bias to generate an accumulation layer in the drain drift region, reducing capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single-gate structure is used, then the device complexity is low, but the operating frequency is limited by gate-drain capacitance
Solution Approach 1:
The single gate is divided into two separate gates (first gate and second gate) with a gap between them. The first gate controls the channel while the second gate controls the drain drift region, allowing independent optimization of each gate's function to reduce gate-drain capacitance and increase operating frequency.
Solution Approach 2:
The boundary between the drain drift region and the body is positioned at a depth below the top surface of the substrate, creating a three-dimensional configuration. This vertical positioning allows the split-gate structure to achieve lower capacitance while maintaining effective control over the current flow path.
2Speed
If the lateral drain extended MOS transistor is designed for higher frequencies, then the operating frequency increases, but the resistance increases reducing power efficiency
Solution Approach 1:
Different regions of the transistor are given different doping concentrations optimized for their specific functions: the channel region has one doping level for high-frequency operation, while the drain drift region has a different doping level optimized for low resistance. This local optimization allows simultaneous achievement of high frequency and low power loss.
Solution Approach 2:
The doping concentration in the drain drift region is specifically optimized to balance two competing requirements: sufficient doping to maintain low resistance for power efficiency, but not so high as to reduce the breakdown voltage and compromise high-frequency performance. This parameter optimization resolves the contradiction between speed and energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables higher operating frequencies and lower resistances compared to single-gate transistors, improving power efficiency and system costs.
Implementation Method 1
the second gate provides a constant on-state gate bias to generate an accumulation layer in the drain drift region, reducing capacitance and resistance
Data Source
AI summary
A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.