Split-Gate LDMOS Structure for Stable BVdss and Lower HCI
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Solution Overview
Problem
Conventional BCD technology using metal field plates in LDMOS devices faces challenges with uncontrollable drain breakdown voltage (BVdss) due to interlayer dielectric (ILD) oxide non-uniformity, leading to unstable breakdown voltage and increased hot carrier injection (HCl) effects.
Innovation Solution
The implementation of semiconductor devices with poly field plates (PFP) and split gates formed on a reduced surface field oxide (ROX) layer, which controls the drift region and alleviates HCl injection without requiring precise drift region implantation, thereby stabilizing BVdss and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal field plates are used in LDMOS devices, then the device structure is simple and manufacturing is easier, but the drain breakdown voltage becomes uncontrollable due to interlayer dielectric oxide non-uniformity
Solution Approach 1:
The patent changes the material parameter of the field plate from metal to polysilicon. This material substitution fundamentally alters the electrical characteristics, allowing the field plate to be controlled by voltage applied to the polysilicon gate, thereby enabling precise control of drain breakdown voltage while maintaining manufacturing simplicity
Solution Approach 2:
The polysilicon field plate structure introduces voltage control capability, creating a feedback mechanism where the applied voltage to the polysilicon gate can adjust and stabilize the drain breakdown voltage, compensating for variations in interlayer dielectric oxide thickness
2Ease of manufacture
If metal field plates are used in LDMOS devices, then the manufacturing process is simpler, but the breakdown voltage becomes unstable and hot carrier injection effects increase
Solution Approach 1:
Changing the field plate material from metal to polysilicon fundamentally changes the electrical control parameters. The polysilicon material allows for voltage-controlled operation, enabling stable breakdown voltage and reduced hot carrier injection effects while maintaining ease of manufacture through standard CMOS-compatible processes
Solution Approach 2:
The polysilicon material acts as an intermediary between the control gate and the drift region. It provides a controllable interface that mediates the electric field distribution, thereby stabilizing breakdown voltage and reducing harmful hot carrier injection effects
3Reliability
If poly field plates with split gates are implemented, then breakdown voltage stability improves and hot carrier injection is reduced, but device structure becomes more complex
Solution Approach 1:
The field plate structure is segmented into multiple parts: a main polysilicon field plate and additional split gates. This segmentation allows independent control of different regions, improving breakdown voltage stability and reducing hot carrier injection while the split gates can be integrated into existing CMOS fabrication processes
4Reliability
If poly field plates are used to control the drift region, then leakage is reduced and breakdown voltage is stabilized, but the manufacturing process becomes more complex
Solution Approach 1:
The polysilicon field plate structure serves multiple functions: it controls the drift region, stabilizes breakdown voltage, reduces hot carrier injection, and can be integrated with standard CMOS processes. The split gate configuration allows the same structure to perform both field plate functionality and additional device control functions
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. A gate oxide layer is formed over a high-voltage N-type well region, an N-type well region and a P-type well region. The gate oxide layer includes a first layer portion and a second layer portion. The first and second layer portions have different thicknesses. A main gate is formed on the first layer portion and the second layer portion. At least one split gate is formed on the second layer portion, and the main gate and the split gate extend along an interface between the high-voltage N-type well region and the P-type well region. An inter-level dielectric (ILD) layer is formed over the main gate and the split gate. A plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate are formed. An electrode is formed to contact the connecting features.


