Split Gate Logic Camouflage for IC Reverse Engineering
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Solution Overview
Problem
Reverse engineering of integrated circuits poses a significant threat to the semiconductor industry, as attackers can steal and replicate circuit designs, and existing countermeasures like camouflage circuits are costly and energy-intensive.
Innovation Solution
The SPLIT GATE approach involves distributing logic gates across multiple cell areas, where transistors are split between cell rows, increasing the complexity and effort required for reverse engineering by camouflaging the gate's pattern across neighboring cell areas, without requiring process technology modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If transistors are distributed across multiple cell areas, then reverse engineering difficulty increases, but device complexity increases
Solution Approach 1:
The gate is segmented into multiple transistors distributed across different cell areas. Each transistor is placed in a separate cell area delimited by supply lines, so that the complete gate function is distributed rather than concentrated in one location. This segmentation makes reverse engineering more difficult while maintaining the same logical gate functionality.
2Object-affected harmful factors
If supply lines are placed between cell areas, then gate camouflage improves, but manufacturing precision requirements increase
Solution Approach 1:
Supply lines act as intermediary elements that naturally delimit cell areas and separate transistors. By placing supply lines between cell areas, the patent uses existing structural elements to achieve both camouflage (by separating gate transistors) and maintains manufacturing feasibility (by using standard supply line routing). The supply lines serve as both electrical conduits and spatial separators.
Data Source
AI summary
According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.