Split-Gate IC Memory Cell Layout for Logic Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit (IC) devices face challenges in integrating memory and logic components within a single device while maintaining performance, size reduction, and cost efficiency.
Innovation Solution
The development of an integrated circuit device with a split gate structure, including a source region, split gate structures with floating and control gate electrodes, an erase gate structure, selection gate structures, and gate spacers, which allows for the integration of memory and logic devices on a substrate, enhancing performance and reducing size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory and logic components are integrated within a single IC device, then device functionality and performance are improved, but device complexity increases
Solution Approach 1:
The gate structure is divided into multiple segments including control gate electrode layers, floating gate electrode layers, and erase gate electrode layers. Each segment performs a specific function within the memory cell, allowing complex functionality to be achieved through modular organization rather than a monolithic structure, thereby managing device complexity while enhancing adaptability
Solution Approach 2:
The integrated circuit device combines memory cell devices and logic device transistors within a single substrate, enabling the device to perform both memory storage and logic processing functions. The gate structures serve multiple purposes including control, data storage, and erase operations, reducing the need for separate components and managing overall device complexity
2Area of stationary object
If memory and logic components are integrated within a single IC device, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate structures are arranged in a nested configuration where control gate electrode layers, floating gate electrode layers, and erase gate electrode layers are positioned at different vertical levels and horizontal positions. This nested arrangement maximizes the use of vertical space, reducing the horizontal footprint of each memory cell and enabling higher integration density while maintaining manufacturability
Solution Approach 2:
The patent utilizes vertical stacking of multiple gate electrode layers to achieve higher integration density. By transitioning from a two-dimensional planar layout to a three-dimensional stacked architecture, the device reduces its footprint area while the standardized layering approach maintains manufacturing precision through repeatable fabrication processes
3Reliability
If multiple gate structures are used in the memory cell device, then memory functionality is improved, but device complexity increases
Solution Approach 1:
The gate structure is divided into multiple segments including control gate electrode layers, floating gate electrode layers, and erase gate electrode layers. Each segment performs a specific function within the memory cell, allowing complex functionality to be achieved through modular organization rather than a monolithic structure, thereby managing device complexity while enhancing adaptability
Solution Approach 2:
The control gate electrode layers and floating gate electrode layers are combined within the same memory cell structure to achieve enhanced memory functionality. The control gates enable selective access and programming operations, while the floating gates provide non-volatile data storage, creating a unified structure that delivers both reliability and integrated functionality
Data Source
AI summary
An integrated circuit includes: a source region, split gate structures on opposing sides of the source region, the split gate structures including a floating gate electrode layer and a control gate electrode layer, an erase gate structure between the split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures on outer sidewalls of the split gate structures, and a pair of gate spacers. Each gate spacer is disposed between one of the split gate structures and one of the selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, and is further disposed on an outer side wall of the one of the split gate structures. A lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.