Split-Gate Memory Cell Asymmetric Inclined Charge Accumulation
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Solution Overview
Problem
In semiconductor devices with split-gate type memory cells, the uneven distribution of electrons and holes in the charge accumulating portion leads to increased holes in the insulating film during repeated writing and erasing operations, reducing the retention property of the memory cell.
Innovation Solution
A semiconductor substrate with a third region between two regions, where the control gate electrode is formed on one surface and the memory gate electrode on a lower surface, with a connecting surface that inclines to ensure even electron and hole distribution, using a specific etching process to form a gate insulating film with a charge accumulating portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional split-gate type memory cell is used with a horizontal charge accumulating portion, then the memory cell can perform writing and erasing operations, but the distribution of electrons and holes becomes uneven during repeated operations, causing holes to accumulate in the insulating film and reducing retention property
Solution Approach 1:
The charge accumulating portion is designed with an asymmetric inclined configuration where one end is positioned closer to the control gate electrode than the other end. This asymmetric structure creates a non-uniform electric field distribution that promotes even distribution of electrons and holes during writing and erasing operations, preventing hole accumulation and improving retention property.
Solution Approach 2:
The invention transitions from a conventional horizontal charge accumulating portion to an inclined three-dimensional configuration. By positioning the charge accumulating portion at an angle relative to the control gate electrode, the electric field distribution is optimized in multiple dimensions, enabling even charge distribution and preventing degradation from repeated operations.
2Reliability
If the memory gate electrode is formed at the same level as the control gate electrode, then the structure is simple, but the electric field distribution becomes uneven leading to poor charge accumulation and reduced retention
Solution Approach 1:
The memory gate electrode is positioned asymmetrically at a lower level than the control gate electrode, creating an inclined configuration. This asymmetric vertical positioning optimizes the electric field distribution for charge accumulation while maintaining a relatively simple overall structure that can be integrated into existing memory cell designs.
Data Source
AI summary
A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface (TS1) of the region (AR1), and a memory gate electrode (MG) is formed on an upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2). An end (EP1) of the connection surface (TS3) which is on the upper surface (TS2) side is arranged closer to the memory gate electrode (MG) than an end (EP2) of the connection surface (TS3) which is on the upper surface (TS1) side, and is arranged lower than the end (EP2).