Split Gate Memory Cell Asymmetrical Source Drain Programming
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Solution Overview
Problem
Current non-volatile memory (NVM) devices face scalability issues, program disturbance, and high costs, particularly in split gate structures, which hinder integration with other devices and require improved scalability, speed, and endurance.
Innovation Solution
A semiconductor device with a split gate structure is developed, featuring asymmetrical source and drain regions and a 1.5T cell configuration, utilizing channel hot electron programming and a composite isolation layer to reduce programming current and eliminate the need for ultra-thin tunnel oxides, allowing for smaller cell size and faster programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2T cell structure is used, then data storage capability is achieved, but device area increases
Solution Approach 1:
The patent merges the select transistor and memory transistor into a single integrated structure where the select gate and control gate are formed adjacent to each other over the channel region. This integration allows the cell to achieve 2T functionality while reducing the overall device area by eliminating separate transistor structures and sharing common regions between the select and memory functions.
2Quantity of substance
If split gate structure is used, then device density increases, but scalability issues arise
Solution Approach 1:
The patent applies local quality by forming asymmetrical source and drain regions with different dopant concentrations and depths on opposite sides of the channel. The first source/drain region has higher doping concentration and deeper junction depth compared to the second region, optimizing local electrical properties for both high density and scalability. This localized differentiation allows the structure to maintain performance across different technology nodes.
3Extent of automation
If conventional programming method is used, then data is programmed, but program disturbance occurs
Solution Approach 1:
The patent employs asymmetry in the source and drain region configurations to control carrier injection during programming. The asymmetrical doping profiles and junction depths create different electric field distributions and carrier generation characteristics at each end of the channel, enabling selective programming of the memory transistor while minimizing disturbance to adjacent cells through controlled carrier confinement.
4Ease of manufacture
If integration with logic devices is pursued, then cost efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent achieves universality by designing a split gate structure that can function as both a memory device and be integrated with logic circuits on the same substrate. The select gate and control gate configurations allow the same basic structure to serve multiple functions, enabling cost-effective integration without requiring entirely separate manufacturing processes for memory and logic portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances scalability, reduces program disturbance, and lowers costs by enabling smaller, faster, and more reliable memory cells that can integrate with logic and other devices on the same chip, improving endurance and programming efficiency.
Implementation Method 1
utilizing channel hot electron programming
Data Source
AI summary
Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.