Split-Gate Nonvolatile Memory Cell Structure for Density and Complexity Reduction
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Solution Overview
Problem
Existing nonvolatile memory cell structures, such as AND-type arrays with floating gates, require complex fabrication processes and high operating voltages, leading to restricted read operations and excessive voltage control lines, limiting cell density and data storage density.
Innovation Solution
A non-diffusion-junction split-gate nonvolatile memory cell structure with a semiconductor substrate featuring spaced-apart floating gates and control gates, where each control gate is capacitively coupled to a pair of floating gates, forming subcells, and assist gates are used between adjacent subcells to control channel regions, eliminating the need for independent voltage control lines and allowing bi-directional operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AND-type arrays with floating gates are used, then nonvolatile memory functionality is achieved, but fabrication complexity and operating voltage requirements increase
Solution Approach 1:
The control gate is divided into two separate control gates, each independently controlling one region of the channel. This segmentation eliminates the need for complex voltage control lines required by shared floating gate structures, as each control gate can be independently controlled with simpler voltage lines.
Solution Approach 2:
The split-gate structure enables the memory cell to perform multiple functions (program, erase, read operations) with simplified voltage control. The same basic control gate structure can be used for different operations by applying different voltage combinations, reducing the need for specialized control lines for each function.
2Quantity of substance
If shared floating gates are used in AND arrays, then cell density is increased, but the number of voltage control lines increases excessively
Solution Approach 1:
By segmenting the control gate into two separate gates, each control gate can independently control its associated floating gate region. This allows for simpler voltage control lines that don't need to carry multiple voltage levels simultaneously, reducing the complexity of voltage control infrastructure while maintaining high cell density.
3Ease of operation
If diffused junctions are used in memory cells, then channel control is achieved, but manufacturing complexity increases
Solution Approach 1:
The invention extracts and removes the diffused junction elements from the memory cell structure, replacing them with a non-diffused channel region controlled by the split-gate structure. This eliminates the complex diffusion processes required to create junctions while maintaining effective channel control through the gate electrodes.
Solution Approach 2:
The mechanical/diffusion-based junction formation process is replaced with an electric field-based control mechanism. Instead of using physically diffused dopant regions to control the channel, the invention uses electric fields from the control gates to control channel conduction, simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies manufacturing, increases cell density, and improves data storage density by reducing the complexity of voltage control and enabling efficient electron flow through non-diffused channel regions, allowing unified control of subcells and assist gates.
Implementation Method 1
Each control gate is located between a first floating gate and a second floating gate, and is capacitively coupled to the first floating gate and the second floating gate
Data Source
AI summary
Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.